I wrote a testbench for my code but while elaborating the design I have this error
# ** Failure: (vsim-3807) Types do not match between component and entity for port "p_in".
# ** Failure: (vsim-3807) Types do not match between component and entity for port "p_out".
This is a bit of a guessing game, as you only posted a snippet, not the whole code including the library definitions.
My guess i that one file uses numeric_std and the other uses std_logic_arith. They both declare the unsigned type and thus, they are different, and incompatible, types.
Are you sure you have compiled the source files without error? It is easy to compile the wrong file, forget to compile a file, or fail to compile a file while missing the errors. In each case, the older results from previous compiles will be used.