why types dont match?

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JKR1

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I wrote a testbench for my code but while elaborating the design I have this error
# ** Failure: (vsim-3807) Types do not match between component and entity for port "p_in".
# ** Failure: (vsim-3807) Types do not match between component and entity for port "p_out".
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but types of the component and the entity are the same,I dont know why this error is happening???
here is the entity :
Code: 
entity x1 is
generic (m,n : Integer := 64);
port(clk : in std_logic;
     p_in : in unsigned(7 downto 0);
     p_out : out unsigned(7 downto 0));
end x1;
and here is the component :
Code: 
COMPONENT x1
    PORT(
         clk : in  std_logic;
         p_in : in  unsigned(7 downto 0);
         p_out : out  unsigned(7 downto 0)
        );
    END COMPONENT;
I would appreciate if somebody help me.
 

Perhaps because you'v declared a generic in the entity, but not in the component.
 

This is a bit of a guessing game, as you only posted a snippet, not the whole code including the library definitions.
My guess i that one file uses numeric_std and the other uses std_logic_arith. They both declare the unsigned type and thus, they are different, and incompatible, types.
 
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    JKR1

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Are you sure you have compiled the source files without error? It is easy to compile the wrong file, forget to compile a file, or fail to compile a file while missing the errors. In each case, the older results from previous compiles will be used.
 

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