why transmission gate is not prefered for layouts and schematics ?

[ABwag]

I have come across some schematics in the libraries i m working . I have seen that direct inputs are not given to the transmission gate ..they have given the output of inverter to the drain or source of trasmission gate. why they have done that? is it that we cannot give direct inputs to drain?

and also why transmission gates are not prefered from layout point of view?

 

[erikl]

Usually TG inputs are directly connected, but for circuit function reasons there could be an inverter in front of the proper TG input, s. e.g. p. 4 of the following PDF: View attachment Transmission_Gates.pdf

On the other hand I've more often seen inverters following the output of a TG, in order to have better drive (fan-out).

I don't see that transmission gates are not prefered from layout point of view - on the contrary: where their output drive is sufficient, they can save a lot of silicon area. Check e.g. multiplier arrays.

 

[dick_freebird]

This may have to do with protecting ignorant library users
from bad things such as the unmodeled / badly modeled
delay of cascaded tgates; built-in buffering fixes that.
Maybe this is not the tradeoff you'd have picked if you
were doing the design full-custom with SPICE and good
parasitics extraction. But library developers are stuck
with a full spectrum of client cluefulness and have to
make the dummies, as well as the experts, succeed.
So you get things like double-buffered nand3_1 gates
and no unbuffered version, like it or not.

 

[ABwag]

i asked a guy at my work . He told me that we cannot give inputs to the transmmission gates directly bcoz it forms a variable capacitance at the input. so its given through an inverter so that it doesnt form a variable capacitor..
so how much correct is his explaination?