Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
Do you mean wrappers according to a test standard: like IEEE 1500 or just DFT insertion when doing synthesis ?
I think you are speaking about the second. In fact scan insertion deals about making a serial scan chains wich are tested by shifting data serially.
The synthesizer insert scan flip-flops instead of ordinary flip-flop where there are additional test pins, and then make the connection between those flip-flops.
Thanks Maulin, Vamsi and DFT_designer.
This is about insertion of wrapping flops in DFT modules.
@vamsi1255,
If we are concerning coverage here, why we are not inserting wrapping flops for all the blocks which satisfy the 'ports directly connected to combo logic' criteria? I have the question here, we are using this concept only for a few blocks. How we are generally deciding this in a design?
@DFT_designer,
I understand the scan concept. What my question is why we are inserting dedicated wrapper flops for some blocks? Is it related to coverage? Or to bypass a particular block? I am not much clear about the reason.
If the block is a reuse block and if designers are not worried of coverage, they will ignore wrapping.
May be they don't want to blow up the area unnecessarily. But in general good practice is to insert wrappers.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.