why this line have a syntax error in modified booth multiplier code?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------
entity mdboothmul is
port(mpcd,mplr : in std_logic_vector(3 downto 0);
result : out std_logic_vector(7 downto 0);
clk : in std_logic);
end entity;
--------------------------
architecture mdboothmul_arch of mdboothmul is
signal acc : std_logic_vector(7 downto 0):="00000000";
signal tmpcd : std_logic_vector(7 downto 0);
tmpcd(7 downto 4) <= (others => '0'); ---???
tmpcd(3 downto 0) <= mpcd;
signal tmplr : std_logic_vector(4 downto 0);
tmplr <= mpcd & '0' ; ---??
begin
process(clk)
--variable tmpcd : std_logic_vector(7 downto 0);
--tmpcd(7 downto 4) := (others => '0');
--tmpcd(3 downto 0) := mpcd;
--variable tmplr : std_logic_vector(4 downto 0);
--tmplr := mpcd & '0' ;
variable temp : std_logic_vector(7 downto 0):="00000000";
begin
if (clk'event and clk='1') then
for i in 0 to 2 loop ---?
if (tmplr(i+2 downto i) = ("000" or "111")) then temp := "00000000";
elsif (tmplr(i+2 downto i) = ("001" or "010")) then temp := tmpcd;
elsif(tmplr(i+2 downto i) = "011") then temp := tmpcd(6 downto 0) & '0';
elsif(tmplr(i+2 downto i) = ("101" or "110")) then temp := tmpcd(6 downto 0) & '0';
elsif (tmplr(i+2 downto i) = ("101" or "110")) then temp := not(tmpcd)+'1';
elsif (tmplr(i+2 downto i) = "100") then temp := not(tmpcd(6 downto 0) & '0') + '1';
end if;
i:=i+2; ---??

end loop;
acc <= acc+temp;

end if;
end process;
result <= acc ;
end mdboothmul_arch;

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tmpcd(7 downto 4) <= (others => '0'); ---???

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TrickyDicky said:

You also cannot modify a loop variable inside the loop - the loop var is considered static and cannot be modified - it increments deending on the range you set. So it goes 0,1,2 in that order. If you specified 2 downto 0, it would be 2, 1, 0.

Anyway - Your code looks too much like a software program that will generate a lot of logic. this will result in a slow maximum frequency. Why not simply pipeline the algorithm without a loop?

I also recommend you dont use variables!

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signal a :std_logic_vector(3 downto -1);

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for i in 0 to 1 loop
dir := Y(2*i-1);
sht := Y(2*i);
add := Y(2*i+1);

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------
entity mdbooth is
port(mpcd,mplr : in std_logic_vector(3 downto 0);
result : out std_logic_vector(7 downto 0);
clk : in std_logic);
end entity;
--------------------------
architecture mdbooth_arch of mdbooth is
signal tmpcd : std_logic_vector (7 downto 0);
signal tmplr : std_logic_vector (3 downto -1);
signal nottmplr :std_logic_vector (3 downto -1);
signal acc : std_logic_vector(7 downto 0);
begin
nottmplr <= not(tmplr)+1 ;
process(clk)
variable dir,sht,add : std_logic :='0';
variable a,b,c : std_logic_vector(7 downto 0);
variable temp : std_logic_vector(7 downto 0);
begin
if(clk'event and clk='1') then
for i in 0 to 1 loop
dir := mplr(2*i-1);
sht := mplr(2*i);
add := mplr(2*i+1);
case dir is
when '0' => a := tmplr;
when others => a := nottmplr;
end case;
case sht is
when '0' => b := "00000000";
when others => b := a&'0';
end case;
case add is
when '0' => temp := b;
when others => temp := a;
end case;
end loop;
end if;
acc <= temp+acc;
end process;
result <= acc;
end mdbooth_arch;

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I dont think you quite understand what a for loop does - when it is synthesised, it unrolls the loop and creates parrallel hardware. Your code still looks like software.

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TrickyDicky said:

I dont think you quite understand what a for loop does - when it is synthesised, it unrolls the loop and creates parrallel hardware. Your code still looks like software.

I highly suggest you re-write the code - this time with no loops and no variables.

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FvM said:

Furthermore, in the present code nothing is unrolled, the second iteration overwrites the result of the first. It's just a useless loop.

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fahim1 said:

I would really appreciate if u help me what can I do to get that point of view for writing codes.

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fahim1 said:

and for the program variables should be replaced with what?and whats wrong with using variables/.?

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FvM said:

temp is set in each iteration. Only the last value is kept, so any calculation result from previous iterations is lost.

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ads-ee said:

Knowing digital design and knowing how to draw a schematic before writing code would be the right point of view. If you can't describe the circuit using a schematic you shouldn't be writing code (this is why most software types write bad VHDL/Verilog descriptions, because they start by designing the code, without designing the hardware first).


why? ... this is why.


For loops in software are temporal (sequences in time), for loops in HDLs are spatial (parallel copies with different indices).

Until you really understand VHDL you should only be using signals and no for loops. When you have that mastered then add for loops followed by variables (and you only need to use those sparingly)

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fahim1 said:

some algorithms are too big and its impossible to draw aschematic and write the code according to it,in these cases what can I do?
and assume that I wrote A code how can I find that its behavioral or structural??
thanks

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