why this bandgap vary with temperature seriously ?

[jake]

Who can tell me why this bandgap voltage vary with temperature seriously? That is, at room temperature, the bandgap voltage output is 1.2074v, however, at 80°C the output voltage is 2.1099v. Here, some transistors are work abnormally.

 

[Btrend]

r u sure N1 & N3 are in the same potential in ur ckt ?
in bandgap design, the PTAT generation is formed by Vbe1=Vbe2+Iptat*R,
but I don't see u let Vn1=Vn3.

 

[Fom]

Your circuit is illegible. I can't recognize sizes of some PMOS transistors 6u or 8u.
Where is your Output? VREF?
But if your R2 r=0 how you can get 1.2V. It should be just Vbe of Q1 PNP. For R1 r=???.

 

[lijun_sun]

i think you didn't find the best point of bg.

 

[bamboo]

jake,
As Btrend asid, I think you should check if VN1=VN3
in your circuit. And in your circuit, NPM-1 and NPM-2 have the same w/l ratio ,but one is marked as 30uA and the other maked 2.5 uA ? It 's not resonable for me.

 

[jake]

Hi Btrend,

I know that N1&N3 must in the same potential, and I ensure this by the cascode amplifier, they are in the same potential, just 0.3mv difference between them. I find the currents in MPB1 and MPB2 increase with temperature seriously, why?
Hi Fom,
Sorry, I reupload the circuit. Yes, my output is the Vref, and the resistors are not equal zero, they are rnwsti resistors of TSMC. The size don't be displayed.

Hi lijun_sun,

Do you think where is the best point of bg in my circuit?

 

[jake]

jake,
As Btrend asid, I think you should check if VN1=VN3
in your circuit. And in your circuit, NPM-1 and NPM-2 have the same w/l ratio ,but one is marked as 30uA and the other maked 2.5 uA ? It 's not resonable for me.

Dear bamboo,
Sorry for the illegibile circuit, please look at the new unpload one. And this structure is derived from the attechment paper.

 

[bamboo]

Dear Jake,
Based on the paper ,
Vbg= Vbe2+N(R2/R1)ln[M(N+1)]*Vt
In your circuit R2/R1=7.4 , N=1 .
So you should let M to be about 16 in order to get the zero temperature coefficient.
when Vbe2 has temp coefficient -2.2mV/C and Vt has +0.085mV/C
because I didn't see the ratio of bipolar in your circuit.
Maybe you should check it first

 

[Btrend]

I find the currents in MPB1 and MPB2 increase with temperature seriously, why?

Because as temperature increasing => Vbe decreasing => Vgs of MPB1 is increasing => Impb1 is increasing
But how serious situation u had encountered ? 30uA to 300uA !?

 

[jake]

Dear Jake,
Based on the paper ,
Vbg= Vbe2+N(R2/R1)ln[M(N+1)]*Vt
In your circuit R2/R1=7.4 , N=1 .
So you should let M to be about 16 in order to get the zero temperature coefficient.
when Vbe2 has temp coefficient -2.2mV/C and Vt has +0.085mV/C
because I didn't see the ratio of bipolar in your circuit.
Maybe you should check it first

Dear bamboo,
In fact the Vbe2's temperature coefficent is just -1.89mV/C,not -2.2mV/C in my case. so M=8, right ? This can get a zero temperature coefficient.

 

[Fom]

Let's calculate
N(R2/R1)ln[M(N+1)]*Vt = 1*[(185/250)ln(8*2)]*Vt = 2.05*Vt
Temperature coefficient 2.05*0.085mV/C = +0.1744mV/C.
But temperature coefficient of Vbe2 is -1.89mV/C. One order higher!!!

 

[ambreesh]

I would suggest that you see the condition of your transistor (PMOS) whoes gate is connected to ground near N7.
When I was trying to impement the same, it was just crazy to get the transistor M6 (as mentioned in the paper) to remain in saturation.
I had mailed the authors also, regarding gate connection of M6 asking if it needs to be ac ground. But no reply
Node6 in the paper must sit at VtM9+Von. Node5 potentila is decided gate of M6 so it would be VtM6+VonM6

 

[jake]

I would suggest that you see the condition of your transistor (PMOS) whoes gate is connected to ground near N7.
When I was trying to impement the same, it was just crazy to get the transistor M6 (as mentioned in the paper) to remain in saturation.
I had mailed the authors also, regarding gate connection of M6 asking if it needs to be ac ground. But no reply
Node6 in the paper must sit at VtM9+Von. Node5 potentila is decided gate of M6 so it would be VtM6+VonM6

Dear ambreesh,
you are right, in this structure, from my simulation, I find that I can't guarantee the transistor M9(mentioned in the paper) work in the right state. The potential of Node6 is less than VtM9+Von. That is, the transistors of M8 and M13(mentioned in the paper) sometimes work in the linear. So the question may be in the amplifier. But I have tried to remove the cascode transistors M6 and M7, the problem doesn't disappear.

 

[ambreesh]

Dear Jake,
If we are observing an increse in reference voltage with temperature one thing is for sure the feedback is not in control.
U, mw and all others who have participated in the discussion would agree that Vbe would decrease with increase in temperature. So if Vref is increasing means we have an increase in the current in those legs. As only increse in the current would lead to increse in Vbe and also IR drop.
We need to find out why is the current incresing in the legs. And then take care of the responcible element.
Hope it helps