Why they are in linear region?

[wjx197733]

Hi, all:

I simulate the circuit of the example 6.3-1 of the book writed by Allen use Hspice.
At first, I make VDD=5V and VSS=0V. When I do DC analysis, I find when the both of the gate of M1 and M2 were applied 2.5v, M8, M5, M7 were in linear region.

I do not konw why and how to correct it.

At the same time I find there have no OP analysis in most examples in this book,

 

[eng_Semi]

Can u attach the circuit ??

 

[wjx197733]

Now I attch the circuit, I hope somebody can help me

 

[Hughes]

What is the bias current you set?
Maybe you set the bias current too large. Try a smaller one.

 

[wjx197733]

But in the example, the bias current is 30uA.

 

[Karthikeya]

hi
wht are the design specs you used? it seems that u have not chosen the right value of input transistors M11 and M12. check the design once again.
simulate the dc transfer characteristic in buffer mode and choose the right op point.

 

[nandu_r]

I am not able to find M8, M5, M7 in your attached schematic
But looking at the circuit I can say
1) tail current source(M15) may be in linear region (since differential pair are not big enough to supply the curent, that why amplifier malfunctions)
2) since this topology supposed to have reasonably good gain, systamatic offset may play a dominent role in driveing the transistor in tol linear region (this may be because current variation in the defferential pair since they see different vds.)