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static power is camparing with dynamic power which is normally the digital clock switch power.
Static power is the power when the digital circuit is power down. Because of the sub-threshold conduction, there is current following through VDD to GND. That's the static power
Power consumed when the output or input are not changing or rather when clock is turned off. Normally static power dissipation is caused by leakage current. (As we reduce the transistor size, i.e. below 90nm, leakage current could be as high as 40% of total power dissipation).
Remember one thing, in small geometries, the treshold voltage isn't decrease so much as suppl voltage, therefore the static power dissipation increases, because the gates could be made high impedance like in techologies with larger suppl voltages. quiesent currents in gates in power dowb node could be in A range for large digital chips an low voltage and small geometries.
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