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Why the open loop gain of LDO is less than 1??

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Analog_starter

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Hi all,

I have simulated a LDO's open loop frequency response (break the loop
at Vfb with ac input), and found its gain was about -40dB@DC. The
error amplifer is a two stage op with open loop gain 65dB@DC, but the
gain will reduce to -40dB once adding the PMOS power transistor into the loop.
My questions are:
1.Should the loop will stable because the open loop gain is alway below 1?
2.But will the LDO's performance be very poor?
3.Why it also can output the correct value (input 3.3v output 2.5v) when the open loop gain is smaller than 1?
4.How can I optimize this curcuit?
5.If the LDO's output is 2.5v, must I adjust it to accurate value in tt 25C case? Is 2.52v also ok?
6.I simulated the startup case, and found its final stable output is not 2.5v when power up whatever several nano seconds (output is about 2.8v) or several mil seconds (output is about 1.8v) . Is it means there are some issues for startup the curcuits?

Thanks a lot!

Best Regards
Analog_starter
 

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