Why the ADC experimental result is so bad?

[pikky]

I designed an ADC , in simultion, it acquired 1Gsamples with the 8 bit resolution, after fabricated in 0.18um process, the experimental result is much worse.

Can anyone tell me the reason?
Or what restrict the performance of an analog circuit after the fabrication?

Thans a lot.

 

[erikl]

Bad layout.

 

[pikky]

But I have done the post simulation and run the corner.

Bad layout.

 

[erikl]

Bad models, then. Not a mature process? How many generations of the model files?

 

[jayanth.neo]

First, I would like to know what was the test bench setup and how pure was the input signal. The distortion in the input signal in addition to improper reference for the ADC will definitely make the ADC testing bad and make the measurements look worse.

The above conditions are true if ur ADC was laid out properly and had no manufacturing issues like others pointed out.

Please search and refer ADC testing methods.

 

[pikky]

Do i need to do the Monte-carlo simulation?

First, I would like to know what was the test bench setup and how pure was the input signal. The distortion in the input signal in addition to improper reference for the ADC will definitely make the ADC testing bad and make the measurements look worse.

The above conditions are true if ur ADC was laid out properly and had no manufacturing issues like others pointed out.

Please search and refer ADC testing methods.

 

[watersky]

yes,I identify with viewpoint of jayanth.neo. you should confirm your testbench is right and entireness. for example the information of encapsulation ans so on. your PCB board is good too.