anilineda
Member level 3

Hi, i am a beginner just started learning Systemverilog. while i am trying a small example mentioned in textbooks
result is shown in picture
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I am mistaken , macros working properly. now the question is argument 'r' is displaying some symbol, but it is supposed to display a true value.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 `include "macro.h" //macro included class exercise1 ; rand bit [3:0] addr; // a simple class rand bit [7:0] data; constraint cb{addr>2 ; addr < 5 ;} endclass module test; exercise1 p; // on object created initial begin p=new(); // allocated memory space and defaulted to 0. `SV_RAND_CHECK(p.randomize()); $display("next"); `SV_RAND_CHECK(p.randomize()); $display("data = %0d, address = %0d", p.data,p.addr); `SV_RAND_CHECK(p.randomize()); $display("data = %0d, address = %0d", p.data,p.addr); `SV_RAND_CHECK(p.randomize()); $display("data = %0d, address = %0d", p.data,p.addr); `SV_RAND_CHECK(p.randomize()); $display("data = %0d, address = %0d", p.data,p.addr); end endmodule // a separate file with the file name "macro.h" `define SV_RAND_CHECK(r) \ do begin \ if ((r)) begin \ $display("%s:%0d: Randomization passed "%s"", \ `__FILE__, `__LINE__, r); \ end \ end while (0)
result is shown in picture

- - - Updated - - -
I am mistaken , macros working properly. now the question is argument 'r' is displaying some symbol, but it is supposed to display a true value.
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