Why SPI is needed

[fragnen]

Why is serial protocol like SPI is needed? Cannot we send the same data by a parallel interface instead of a SPI serial interface?

 

[dick_freebird]

Consider the impact to PCB / module routing when
data bus widths are 36 or 72-wide (times 2, if
differential such as DDRx), vs a 2 or 3 wire
serial (which can be shared among multiple clients).

Parallel busses of this sort, if not a current-limited
differential with a controlled impedance, will also
be an EMI and ground-bounce menace, simultaneous
switching of 72 outputs at tens of pF apiece will whack
the ground or supply pretty hard. That can corrupt
data or analog signal at random (-appearing) times.

 

[FvM]

You'd rather ask the opposite question. Which applications need a parallel interface although a serial interface like SPI is preferred in terms of pin count and PCB space?

Limits are however shifting, 30 years ago printers used parallel Centronics, hard disks parallel ATA and SCSI interface, you know what todays popular computer interface standars are.

 

[dpaul]

Why is serial protocol like SPI is needed?
Cannot we send the same data by a parallel interface instead of a SPI serial interface?

Serial interfaces are really fast these days thanks to advances in various PHY layer technologies. As you save a hell lot on pin count by not using a parallel interface, this in turn saves die area for a FPGA/ASIC combined with space in case of PCBs. The end effect is that save product cost, which is the ultimate goal for any product.

 

[fragnen]

Parallel busses of this sort, if not a current-limited
differential with a controlled impedance, will also
be an EMI and ground-bounce menace, simultaneous
switching of 72 outputs at tens of pF apiece will whack
the ground or supply pretty hard. That can corrupt
data or analog signal at random (-appearing) times.

What do you mean by :
Parallel busses of this sort, if not a current-limited
differential with a controlled impedance, ?

Please clarify.

When the same parallel data of 32 bit is sent in a serial bus it will require a higher serial frequency and that will whack the power or ground in a similar fashion as in parallel transfer. How are you saying then a serial bus will help avoiding whacking of power and ground and hence advantageous?

Thanks for the reply.

--- Updated Apr 28, 2021 ---

Serial interfaces are really fast these days thanks to advances in various PHY layer technologies. As you save a hell lot on pin count by not using a parallel interface, this in turn saves die area for a FPGA/ASIC combined with space in case of PCBs. The end effect is that save product cost, which is the ultimate goal for any product.

The area savings appears not to be of significant amount as if a 16 bit interface is turned to be a single bit interface, the area saving of routing of 15 wires is not of significant amount. How is the advantage of area saving is happening then?

Thank you for the reply.

 

[ThisIsNotSam]

The area savings appears not to be of significant amount as if a 16 bit interface is turned to be a single bit interface, the area saving of routing of 15 wires is not of significant amount. How is the advantage of area saving is happening then?

but interfaces are not wires. they require IOs, which are typically very big circuits. they also require careful power distribution and tend to operate at voltages like 1.8V or 3.3V which are not core voltages in CMOS for almost 2 decades now. every time one of these chunky circuits flip, the IO ring bounces. If 16 flip at the same time, it bounces a lot. a hell lot.

 

[danadakk]

Some advantages listed here -

Serial Peripheral Interface - Wikipedia

en.wikipedia.org

Chaining, reliability (less connections) to name a few....


Regards, Dana.

 

[fragnen]

but interfaces are not wires. they require IOs, which are typically very big circuits. they also require careful power distribution and tend to operate at voltages like 1.8V or 3.3V which are not core voltages in CMOS for almost 2 decades now. every time one of these chunky circuits flip, the IO ring bounces. If 16 flip at the same time, it bounces a lot. a hell lot.

This is a case where SPI is used in SOC interface where in the PCB where this SOC will sit with interact through the SPI I/O instead of 16 bit interface. How will this apply when a block in the SOC interacts with another block using SPI instead of a 16 bit parallel interface?

 

[ads-ee]

This is a case where SPI is used in SOC interface where in the PCB where this SOC will sit with interact through the SPI I/O instead of 16 bit interface. How will this apply when a block in the SOC interacts with another block using SPI instead of a 16 bit parallel interface?

fragnen once again you are not supplying all the information to answer your questions. Not worth going down the rabbit hole.

 

[ThisIsNotSam]

This is a case where SPI is used in SOC interface where in the PCB where this SOC will sit with interact through the SPI I/O instead of 16 bit interface. How will this apply when a block in the SOC interacts with another block using SPI instead of a 16 bit parallel interface?

you are confusing buses with interfaces.

 

[dpaul]

@fragnen
I have answered the original question (#4), and !Sam has provided you the answer (#6) to your counter question.
Now I just pull out of this thread!

 

[dpaul]

How will this apply when a block in the SOC interacts with another block using SPI instead of a 16 bit parallel interface?
For intramodule communication within an SoC, you use buses, not interfaces! SPI is an interface. !Sam has answered the Q in #10.

 

[fragnen]

How will this apply when a block in the SOC interacts with another block using SPI instead of a 16 bit parallel interface?
For intramodule communication within an SoC, you use buses, not interfaces! SPI is an interface. !Sam has answered the Q in #10.

What will be the need to use a SPI bus for intramodule communication instead of a parallel bus?

 

[dpaul]

@fragnen,
I doubt you English understanding ability. Because you are asking the same Q again and again with total disregard in trying to understand what others have said or tried to explain.
I wash my hands off, bye!

 

[dick_freebird]

What do you mean by :
Parallel busses of this sort, if not a current-limited
differential with a controlled impedance, ?

Please clarify.

When the same parallel data of 32 bit is sent in a serial bus it will require a higher serial frequency and that will whack the power or ground in a similar fashion as in parallel transfer. How are you saying then a serial bus will help avoiding whacking of power and ground and hence advantageous?

Consider LVDS - 4mA current source output, so no
more than 4mA per pair will be thrown to GND or
VDDIO regardless of loading.

Consider "HC" series CMOS -4mA @ 400mV VOL;
that's about a 100 ohm Rout and the current from
a single output at start of transition might be (say)
1.8V/100 ohms or 18mA, at high edge rate.

Now take 16 of those and switch all outputs low
from high. That's an abrupt 288mA of ground
current. SSI chips like octal bus transceivers with
"24mA" buffers (capable of throwing ~ 100mA
per driver) and 8 channels even have input reswitch
problems if heavily loaded and poor ground
return.

Across bondwires this could turn into an on-chip
VSS excursion of tens to hundreds of mV. Certainly
a jitter contributor, possibly an input logic level
violation depending on how much loading, how
poor decoupling etc. More ground and supply
bonds will help, on-chip bussing and excessive
bond wire length will hurt.

Parallel routing consumes board surface area.
Take (say) 50 mil trace, 50 mil space (far from
leading edge, but whatever). Each trace consumes
100 mils. A 16-wide data bus would be 1600 mils
wide times run-length. That would make the
routing larger than the chip in most cases.

Thanks for the reply.

--- Updated Apr 28, 2021 ---

The area savings appears not to be of significant amount as if a 16 bit interface is turned to be a single bit interface, the area saving of routing of 15 wires is not of significant amount. How is the advantage of area saving is happening then?

Thank you for the reply.