why source bypass cap can cause low-frequency oscillations?

[vale]

In GaAs FET bias network, a source resistor is used to set the DC point and bypassed by an cap. Why is it said that this cap may cause oscillation?
Another question:
Is it necessary to make the FET unconditional stable (such as add a parellel resistor at output) before matching networks design? Is it safe that just chosing Γ_s and Γ_l away from stable circles?

 

[Soben]

Re: why source bypass cap can cause low-frequency oscillatio

I will give u my idea here,

First this bypass Cap is a feedback Cap, that sets a pole and zero in your closed loop gain responce. Thing is usually the value is chosen to be quite big but if u work in MCW that cant be the case due to low Frequency resonance. Also all SMD MCW caps after a specific frequncy deviate from the ideal responce and behave like RLC circuit so there is also inductance in series with your Cap. That means if u dont carefully sellect your CAP, with high SRF from your operation frequency, like 10*Fop u may get in trouble. Also that feedback cap may create such a phase shift at low frequencies that you get a resonance.

Btw never all this happen to me so dont get panicked But there is always the chance.

That resistance u want to add at the output has an effect on the gain of your amp but it will shift your Output stability cyrcles out of the Smith Chart.
U may also play with your High frequency Decoupling caps at the RFC. That helps some times. I suggest u try to move the Stability circles out of the Smith Chart as possibe. But if u operate as a certain frequency and u guarantee Zl and Zin for stable operation i dont think u will have any problems at all.