Why PMOS used in LDO more than NMOS?

[hktk]

nmos ldo

due to the lower Rout?

 

[vfone]

ldo nmos

Lower Ron resistance
https://www.fairchildsemi.com/ms/MS/MS-556.pdf

 

[bunalmis]

pmos over nmos for ldo

At the negative ground PMOS has advantages becouse,

NMOS Gate voltage must be high than Vin (Vin + Vthreshold)

But at the Pmos Vthreshold voltage lower than Vin.

But if you use positive gnd NMOS has advantages.

 

[hktk]

nmos ldo compensation

but in Low Drop-Out Regulator, Pmos is used to achieve lower voltage drop. how can Pmos do that other than Nmos?it seems that lower Ron is not the reason.

 

[andy2000a]

what nmos is used for ldo output device

I have another problem is
if use OPA + pmos for LDO , pmos output
use "drain" output ,
I think use Nmos have low output impedance

 

[lastdance]

n mos signal gain

when you have VIN about the same as VOUT, PMOS is the natural choice. NMOS must have a VGS drop which means VOUT cannot be nearer to VIN by less than VGS.

 

[sergeyr77]

nmos vs pmos regulator poles

Use the same trend as in CMOS: PMOS pass VDD well (precharge to VDD) and GND bad, NMOS pass GND well ( discharge to GND) and VDD bad. In this case Vin is VDD. You can make Ron as low as you want.

 

[leonwang]

ldo pmos nmos

I agree with sergeyr77.

As a switch, PMOS often let the VDD pass.
However, NMOS let the gnd pass.

 

[kwkam]

pmos ldo

I have any point of view, use NMOS in LDO more easier latchup than PMOS.

 

[alchen77]

common source pmos regulators

I have any point of view, use NMOS in LDO more easier latchup than PMOS.

can you explain more clear?? thanks very much!

 

[Vamsi Mocherla]

pmos nmos 出力抵抗

PMOS device is usually used in a common source configuration and hence a Low voltage drop of VDSsat. While NMOS device is used in a Sorce follower configuration and hence causes a VGS drop in additional to the VDSsat required to drive it. Hence PMOS is the best choice.

 

[yuiko]

why do pmos is used as pass transistor in ldo

because you can reduce output voltage with one Vgs

 

[ambreesh]

how is an ldo used

1 A regulator needs to have high efficiency. For LDO' voltage efficiency is more critical. To have more voltage efficiency, difference between Vout and Vin must be less. This can go down to VDsat for a common source configuration rather than source follower configuration. Assumption Vout very close to Vin

2. Example vout =1.8V Vin=5V, use NMOS as pass device, higher mobility, lower W/L thus smaller capacitance, fast responce at output, larger bandwidth. Remember the output swing of the amplifier and the modfied Vth of power MOS and Vout shall decide your overdrive.
All is finally trade off

 

[Tianlei]

voltage drop on pmos

Another thought, PMOS(CS configuration) can provide much more open loop gain than NMOS(CD configuration), so less output error.

 

[yeewong_su]

pmos nmos voltage drop

for pmos can provide the output voltage high as vdd

 

[ambreesh]

voltage drop in pmos

Dear Tianlei,
Their is a catch in that.
your gain is gm *Rout
Rout is paralle combination of feedbak resistors, rds of PMOS and teh load.
Now the load is usually a very small reisstance e.g Iout=200mA Vout=2V then load resistance is 20Ω. (full load case)
Usually one would observe gain reduction in full-load condition

 

[Tianlei]

pass device ldo pmos or nmos

The 20ohm resistance is the DC impedence. In this calculation, AC impedence should be used.
e.g. a 200mA current source is connected to the output of LDO, It s AC impedence is infinite.

My concern is: if using so small AC resistence at the output of LDO, it will move the dominate pole to very high frequency, impact the stability.

 

[ambreesh]

ldo with pmos pass gate

You do use a large cap at output to stabalize your LDO, usually micro farad.
Yes the current source would have ideally infinite AC impedance but the we do have this large cap shunting it.
And a current source having a fixed voltage across it can be replaced by a resistor.
The reduction in error due to large gain one does concider DC gain
If I have lost you point some where please explain that

 

[Tianlei]

what is a pmos used for

First, the gain should be small signal analysis.

AC impedance refer to the small signal impedance, it range from 0 to infinite Hz. We should use this impedance in the gain analysis.
The DC gain should be the small signal gain at 0 Hz.

Current source has the same large signal impedance as resistor, but has different small signal iimpedance.

 

[muldersun]

rds on pmos

PMOS: lower drop-out voltage
If you want to use nmos, you must choose charge-pump circuit.