Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Actually, there are lots of pratical circuit using 3v power suply. The reason for 3.3 V, I think, is because that for the particular process, the gate voltage can be at that value. If you use 0.18u technology, usually, the power suply is at 1.8V.
The process offers a maximum of 3.3V of operation for nominal devices, but you could also design circuitry with less power supply voltage with a tradeoff of reduced stacked transistors and less output voltage swing. Hope this helps
When the Fab scales down for the next technology, the gate oxide thickness in MOS transistors must also be reduced. The big jump was from 0.5um to 0.35um technologies. This was really the first time when gate oxides were reduced below 10nm. At 10nm, the gate oxide can hold off 8Volts so it can easily be used for 5Volts. Since everyone that made power supplies only guaranteed on +/-10%, that meant the MOS must be reliable at 5.5Volts. Two problems : one is that a 10nm oxide when it gets above 8V it starts to tunnel electrons through it. That is how they can be used in EEPROMs and Flash. But worse than this, at high drain voltages hot electrons are injected into the channel and bulk of the Si. These can implant themselevs into the gate ioxide causing unreversible damage (unlike the tunneling case). So the 10nm oxide also had to withstand hot electrons from drain voltages at 5.5V.
OK so we want to shrink to 0.35um. Unfortunately it is not worth shrinking if you do not shrink vertically as well a laterally. Next best oxide was around 7nm. This starts to tunnel close to 7 volts and cannot withstand hot electrons from 5.5V on the drain. So the fab industry said:
"We want to lower the power supply to below 5V" with a big cheesy smile expecting nothing but complete compliance.
The board industry (in particular PC motherboards) said :
"Not frickin likely - in you dreams !"
So the fab industry got extremely upset at this and went off and engineered around it. Two gate thicknesses, 1 to interface with those really mean board people at 5.5V and one just for the boys. 3.6V was chosen as the max to provide enough for high speed drive capability and good immunity to hot electrons. Since the power supply guys live in the eighteenth century the maintained +/- 10% so 3.3V was chosen as centre 3.0V to 3.6V.
Then one day, a fab with enough muscle went to the board guys and said:
"You go 3.3V or you dont get any pentiums"
The board guys then said
"Stuff you we'll go AMD"
To which the fab guys said
"Only kidding! You can stay 5V"
Then one day another fab guy with muscle said
"3.3V or nae Athlons!"
To which the board guys said
"Oops!"
Then all the boards went to 3.3V. The fab guys feeling really pleased with themselves said "Lets shrink to 0.18um and annoy the hell out of the board guys!"
At 0.18um, gate oxides were reduced to about 3.5nm. This oxide can only stand about 2.5V on the drain for hot electrons. So the fab guys went for 2.0V max about 3-4x the threshold voltage. With +/-10% stuck hard, this meant 1.6V to 2.0V so 1.8V nominal.
And then they all went back to start annoying the board guys again.
The boards are still about 3.3V nominally although some chips are still 5V
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
