Why PCI trace on expansion card has 1.5 inch constrain?

[edavio]

max trace lenght for pci signal

According PCI specs, there has max trace length constrain for pci signal on expansion card. It say that pci signal trace on expansion must less than 1.5 inch. I am confusing why it has this constrain. Is it because of timing issue or signal integrity issue? 33Mhz PCI have 10 ns timing budget for propagation delay. Base on my understanding, the signal trace can be as long as 60 inch(as signal speed is 6 inch/ns). It is far beyond 1.5 inch. even, we think about trace on planar board. If I assume that the trace on planar board consume 30 inch, I think it still should has 30 inch trace length budget on expansion board (60 - 30 = 30).

Pls advise!

 

[cesare]

pci bus trace length

You have to take into account what happens on a full loaded PCI bus.

The constraint is for both SI and timing constraint.

 

[edavio]

timing budget for pci

Thanks cesare! Pls explain more. there are voltage level shifter chips between PCI connector with PCI IO chip, pin to pin delay of the level shifter is 200ps. According my understanding, 200 ps delay equals 1.2 inch trace length. At that case, Do I need count this 1.2 inch into 1.5 inch constrain?(that means there is only 0.3 inch routing margin)