Why only Top metal layer should be Low resistance why not ?

[medasunil]

why lower metal has his resistance

Hi All.

Why only top metl layer should be low resistance why not bottm Layers.
I mean viseversa.

Please correct me if iam wrong.
Reason1.Top metal layers width is more than the lower metal layers (R=row*L/A)
if so why should?
Reason2.Top metal layer are uses copper where as bottm layers are alluminum as a cost factor.why?

In general all metal layers are required with low resistance but why this difference in a chip? Why not all metal can have same resistance? What is the logic in this?

Please explain me more

 

[raju3295]

rho + metals

hai medasunil,
good topic, wht goes thru my mind is,, lower metals are used for mostly signal routing and top layers are used for power grid,
so to decrease the IR drop, top layers are made more width,

 

[timof]

lower resistance than aluminium

Why only top metl layer should be low resistance why not bottm Layers.

This is a very good question.

Theoretically, one would want to have all metal layers with low resistance. Practically, there are limitations - cost and technology - that lead to finite metal resistance, and the optimal solution to the problem is to have lower metals with higher sheet rho (sheet resistance), and higher metals with lower sheet rho (sheet rho is volume resistivity divided by metal thickness - so that resistance of metal line of width W and length L is equal to sheet rho times L divided by W).

All metal layers can be made of copper, and copper has much lower resistance than aluminum (~1.7e-6 Ohm*cm vs ~2.7e-6 Ohm*cm). However copper technology is more expensive than aluminum technology, so there is a cost-performance trade-off.

From technology viewpoint, you can make a metal layer very thick (to make sheet rho value lower), but then you can not make metal line very narrow. So if you want to achieve very fine metal pitch (to provide high integration density - i.e. number of devices per unit area), the metal thickness can not be made very large. The solution is - to use thinner (and thus more resistive) metal layers for low layers (i.e. M1, M2, ...) and for local routing, and thicker (less resistive) layers with larger width and spacing for long-range routing on the higher levels.

 

[raju3295]

why resistivity of top metal layers is less

hi timof,
nice & informative explanation you have given,
it would be more helpful to me if u can elaborate on the following words
"optimal solution to the problem is to have lower metals with higher sheet rho" -- i assume rho u mean,, the resistivity,, why it is desired to be more for lower metals. as more rho implies more resistance.

 

[timof]

best metals lead price

it would be more helpful to me if u can elaborate on the following words
"optimal solution to the problem is to have lower metals with higher sheet rho" -- i assume rho u mean,, the resistivity,, why it is desired to be more for lower metals. as more rho implies more resistance.

Yes, "rho" means "resistivity".

What's desired in lower metals is smaller pitch (denser packing of devices), which does not come for free - this requires metals to be thin and thus more resistive.

 

[gharuda]

metal layers for routing

If we consider a chip with many blocks like dsp block, adc block ............
for interconnection within a DSP block we could use a lower metal for routing, since the length of the lower metal will be small if routed with in a block, so the width of the lower metal is reduced, such that resistance does not effect the signal strength or speed.

If a top metal is used for routing with in a block resistance of the interconnect will be less, with the cost of the AREA , if more top level metal are used for interconnection
via1,via2........... comes into picture . and the current density {}

for interconnection b/w different blocks top layer metal is used because they interconnected length are greater .

so lower metal are used for local routing (less area even polysilicon can be used for small connection)
top metal are used for global routing (more area)


{



............____________________ metal1
............_|__________________ metal2


..........._____________________
...........__|__|__|___|__|___|__


if u see in the first case their is only one via between metal 1 and metal2 ,when current flows from metal2 to metal1 or vice versa . The concentration of electron or current density is more at the junction b/w M1 and M2. As the concentration increases the junction might be damaged. Since their is only one path for the current to flow from M1 toM2 the resistance increases.

in the second case more vias is used so . current flow is even distribute b/w M1 and M2. The same thing holds good when active layer (diffusion layer) connected to a metal)

}