Why NMOS has better matching properties than PMOS?

[santhosh.mandugula]

Why NMOS has better matching properties than PMOS?

 

[vijaykarnam]

mismatch is directly propotional to area. PMOS having larger area than NMOS. so, PMOS having higher mismatch..

 

[n1cm0c]

The "normal" (native) Vth of the NMOS is negative. In order to bring it to a positive value one must do an ion-implantation step, where dopant is introduced under the gate to obtain the "correct" (nominal) positive threshold voltage.
This adjustment process step makes the Vth more uniform across the wafer.

Native PMOS has already the negative Vth, and in most technologies no ion-implantation is done to adjust the PMOS Vth. In more modern (sub-nanometer) process both NMOS and PMOS are adjusted, btw.

 

[yxo]

mismatch is directly propotional to area. PMOS having larger area than NMOS. so, PMOS having higher mismatch..

Isn't true!!!

From Alan Hastings "The Art of Analog Layout"

"Consider using NMOS transistors rather then PMOS transisors. NMOS ransistors generally match better then PMOS transistors. Whenever circuit consideration allow, consider using NMOS transistor rather than PMOS transistors".
In other books, i read that this is empiric rule. And precisу explanation in not.

 

[Alan_Nesta]

Agree with yxo.
It is empiric rule.
But PMOS for diff-input-pair still has its merit such as no body-effect, low 1/f noise.

 

[DenisMark]

Indeed PMOS requere additional process steps for making. So non-uniform distribution of dopant on the surface of NWELL gives an increasing of Vth mismatch regarding NMOS.
On the other hand the isolated NMOS in DNWELL has worse mathing properties than NMOS or PMOS.

 

[lylnk]

I don't think this is always right.

You must check the mismatch report provide by foundry!

 

[solidstate]

All technologies that I've worked in had better matching for PMOS than for NMOS (for the same WL); Matching is proportional to 1/sqrt(WL), so the more area, the better. 1/f noise is typically two orders of magnitude better for PMOS devices. Of course, for the same input gm, your PMOS pair will be 3x the W of your NMOS pair (rough avg), improving matching but degrading BW slightly

 

[salerno]

Looking at the matching properties of the transistors, PMOS's have lower matching parameter than NMOS's, that means PMOS has lower mismatches (e.g. offset voltage in a differential pair). To know the reason I suugest to read technical books.

 

[dachuan315]

i thank that different foundry is different.

 

[pit1000]

Quote from "Understanding MOSFET Mismatch for Analog Design" P.Drennan and C.McAndrew (JSSC, v38, N3, march 2003)

 

[suru]

P MOS ARE IS 3TIMES MORE. HENCE.