Why "neck up" diff pair when escaping BGA?

[miner_tom]

Hi,

Having supervised the routing of many boards, I now see that there are capabilities such as in Altium, where it is possible to have a design rule such that the diff pair can "neck down" to a smaller size, to route in a tight area, as in a BGA. These tools also make sure that the characteristic impedance is constant.

My question is, if the diff pair can be made small enough to fit between BGA (or other) balls/pins, then why not keep the diff pair dimensions the same, outside of the area of the BGA? Why not keep the diff pair dimensions the same through out the route? Yes, fab houses have minimum trace widths and gap widths, but if these dimensions can be acceptable under the BGA, then why can they not be acceptable outside the BGA?

Thank You
Tom

 

[dick_freebird]

Yield of fine pitch lines is probably inversely proportional to
the length exposed to manufacturing defects (PR and etch).
Fine lines have more resistance and not much less capacitance.
There are times when you need to push your luck, but every
time is kind of a bad idea.

 

[senilicus]

Your assumption is totally wrong.


Due to the stackup, you can end up with dimension for your diff pair that simply do not fit inside a BGA region. To maintain a tight coupling between the two traces of the diff pair, the tracewidht and clearance inside the BGA area is narrowed down.

This means that the impedance of the diff pair inside the BGA area in not 100 ohms, but as good as it gets.




The smaller tracewidth/clearance will cause a change of impedance.

 

[miner_tom]

Your assumption is totally wrong.


Due to the stackup, you can end up with dimension for your diff pair that simply do not fit inside a BGA region. To maintain a tight coupling between the two traces of the diff pair, the tracewidht and clearance inside the BGA area is narrowed down.

This means that the impedance of the diff pair inside the BGA area in not 100 ohms, but as good as it gets.




The smaller tracewidth/clearance will cause a change of impedance.

Senilicus,

What you say makes logical sense to me. I am only confused by the Altium claims that the characteristic impedance of the diff pair can be maintained in the necked down area. Perhaps there is a tolerance issue, as you say, but Altium does not claim that. Is their claim somewhat bogus?


https://www.youtube.com/watch?v=1n80PMhCZQA

Thank You for your reply
Tom

 

[dick_freebird]

Altium claims that the characteristic impedance of the diff pair can be maintained in the necked down area. Perhaps there is a tolerance issue, as you say, but Altium does not claim that. Is their claim somewhat bogus?

"Can" and "will" are two different things, and "is" yet
another entirely.

 

[andre_luis]

I am only confused by the Altium claims that the characteristic impedance of the diff pair can be maintained in the necked down area

As far as I see in their docs, Altium allows defining different rules for the pair nets so that you can route under the BGA room without being impeded to to that due to violate specifications that meets the required impedance for the pair; therefore, this sounds like as turn around to achieve routing without being warned, not properly a magic feat to maintained impedance characteristics in the necked down area.

Differential pairs are typically routed with specific width-gap settings to deliver the required single-ended and differential impedance needed for that net-pair. While the optimal settings may be achievable for most of the board, there will often be areas, such as under a BGA component, where smaller and tighter width-gap settings must be used. As well as switching the Width-Gap settings interactively (as described above), this requirement can also be achieved by defining multiple differential pair routing rules - a lower-priority rule that targets the differential pair across the board, and a higher-priority rule that targets the differential pair in specific areas. You then target the differential pair in a specific area by defining a Room Definition rule and use that room as part of the scope of a differential pair routing rule - as shown in the series of images below.

Source: https://techdocs.altium.com/display...SwitchingtheDifferentialPairWidth-GapSettings