Why my chip can stablize soon only when GND floated?

[brian_zhong]

I have designed a sigma-delta AD converter, and I am testing it on the user environment, but find the chip need a long time to be stable after power up. please refer to the figure in attachment.

When the GND_module connected to GND_system, data read out by mcu keeps on increasing and needs about 20~30 seconds to stablize. But the data can stablize in 3 seconds if GND_module doesn't connect to GND_system. After power up and the transition time, the chip works well.

I can understand why the chip can work properly when GND_module floated. Although GND_module is floated, the capacitor(10uF) can be charged when SCL/SDA is low(through the ESD protection diode). The potential on this capactor is about (VDD-2*0.5) volt. So the chip can work(i.e. data read out by mcu stablizes in several seconds).

But it's really weird that the chip needs such a long time to be stable.

Some information on this chip may be important:
1. When GND_module floated, if VDD of 5V is applied the chip stablizes in 10 seconds while it need 30 seconds in 3V.
2. Substrate of the chip is P and not connected to GND_module(due to PCB design error). 0.35micron process.
3. the average current(when converting) is about 100uA
4. It seem to stablize quicker without exposure to light

I have been puzzled for couples of weeks and hope you can give me a hand.
Thank you very much!

 

[brian_zhong]

Can someone give me some hints? Thanks

 

[electronrancher]

it's strange, i agree! just to make sure - you do have pullups on SDA/SCL, don't you? This would cause the vdd to charge up much higher than what you mentioned - that's why i ask.

 

[brian_zhong]

Thanks, electronrancher. I did add pullups on SDA/SCL.

Now we are focusing on the light-sensitivity of it. When exposed to strong light, it stablizes at once after power-up with a higher conversion result. When light becomes weaker, more time is needed to settle down and conversion output become lesser. And after the environment becomes dark, the chip needs long time to be stable.

Can it be the defect of manufacture process? We use Charted .35 CMOS with P substrate.

 

[Btrend]

did u ever tried to separate the two power and two gnd with two independent voltage sources?

 

[elantra]

your ic's substrate is floating???
too strange to understand that is is caused by PCB error.

 

[Teddy]

Interesting. I agree with elantra.
Personally I would probe the GND/VDD pins and local power bus to know where those are.
Then I would (with uprobe) supply gnd into the chip to see if it improves or not.
And I would check if there is any leak between VDD/GND.
And if you really want to - send me the database.... I know - just kidding.

 

[yellff]

Do u use multi GND?maybe the multi GND shd be seperated.

 

[manish12]

THERE IS JUST DIFF OF 0.7V CHECK IT .
IT MAY HAPPEN THAT ONE SECTION OF CKT IS OPERATING AT XVOTL
AND CONNECTED SECOND CKT IS OPERATING AT X+0.7 VOLT.
GENERALY , DESIGENER PLACE A DIODE BETWEEN GND AND LINEAR REGULATOER EX 7805 ETC.
AND SENSOR SIDE MAY BE BATTERY DERIVN.

 

[bigbro]

It looks like there is floating node in your database.
If substrate is floating, the floating node would pull up easily.
Also leakage should be increase under high light source.
This is the reason you can reduce stabilized time, I think.