why my buck converter's output is not it has been setted

[cesczhang]

I have designed a buck converter, controlled by current mode PWM controller, the input is 3V, the max duty cycle is 90%, but when I set the output at 2.7V, it can only reach to 2.2V,
anyone knows it , please help,
thanks

 

[leo_o2]

It might enter into drop-out region. Please try to increase input voltage to 4V and check the output again.

 

[cesczhang]

It might enter into drop-out region. Please try to increase input voltage to 4V and check the output again.

the chip can't work under 4V input, it was designed can output 2.7V under 3V input ,because the maximum duty cycle is 90%
the input region is 2.7-3.3. the output was not in oscillation, so the pole-zero location is in the right region, and according to simulation results.the opamp's dc gain is large enough, but the output was not which it had been set, it really confused me.

 

[leo_o2]

D=VO/VIN is only correct for ideal condition. That means no Ron loss.
For actual circuit, power mos will have Ron not equal to 0.
For some dc-dc, the max duty cycle is 100%. Even for this kind of dc-dc, it will enter drop-out region just like LDO.
For 100% duty cycle, PMOS is fully on and NMOS is fully off.

 

[cesczhang]

I just find that the slope compensation range was too wide, maybe this leads the problem

 

[leo_o2]

And pls increase current limit. Maybe it limits actual max duty cycle.

 

[cesczhang]

And pls increase current limit. Maybe it limits actual max duty cycle.

thanks a lot, and actually current limit is high enough
the other question: to avoid drop out, can we add a maximum duty cycle clock

 

[RCinFLA]

thanks a lot, and actually current limit is high enough
the other question: to avoid drop out, can we add a maximum duty cycle clock

The limit is determined by Rs of switching device and Rs of coil based on current requirements. Achieving 0.3 vdc input to output voltage differential is very difficult.

 

[cesczhang]

thank，the problem is resolved