why metastablity state finally changes to the steady state?

After Metastability state finally the output of the flipflop settles to eighter logic high or logic low..how it happens? what is the parameter making it possible to settle to a steady state ?

When the transitions in the clock and the data are close together in time, the flip-flop is forced to decide which event happened first. However fast we make the device, there is always the possibility that the input events will be so close together that it cannot detect which one happened first. It is therefore logically impossible to build a perfectly metastable-proof flip-flop. Flip-flops are sometimes characterized for a maximum settling time (the maximum time they will remain metastable under specified conditions).

Normally you lookup setup and hold times and ensure design meets these criteria.

what is the parameter making it possible to settle to a steady state ?

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A flip-flip has two stable states by design (due to positive feedback), so common sense rather suggests the opposite question: "How can the circuit stay in a metastable state (at least for finite time)?"

To try a mechanical analogy, it's a case of unstable equilibria where the logical level inside the memory circuit stays exactly in the middle between low and high. By the effect of circuit noise, the state flips fastly to either low or high. https://en.wikipedia.org/wiki/Mechanical_equilibrium

As SunnySkyguy explained, the metastable state will be usually triggered by a timing violation, e.g. the input signal of a D-FF is sampled exactly during an edge.

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what is the parameter making it possible to settle to a steady state ?

Click to expand...

A flip-flip has two stable states by design, so common sense rather suggests the opposite question: "How can the circuit stay in a metastable state (at least for finite time)?"

To try a mechanical analogy, it's a case of unstable equilibria where logical level inside the memory circuit stays exactly in the middle between low and high level. By the effect of circuit noise, the state flips fastly to either low or high. http://en.wikipedia.org/wiki/Mechanical_equilibrium

As SunnySkyguy explained, the metastable state will be usually triggered by a timing violation, e.g. the input signal of a D-FF is sampled exactly during an edge.

Basically at the next clock edge(after the flop goes metastable) it detects either a logic 1 or logic 0 at the D input. The Q follows this value. That is why when using synchronizers, it is expected to keep the input to the synchronizer stable for multiple clocks so that in spite of metastability, the correct value is captured.