In one of your previous thread I left You names which You should put into google... But OK.
The two types of mismatches exists - statistical related to fluctuation of device dimensions, gate oxide thickness, dopants - and systematic caused by gradients of dopants density, polysilicon and SiO2 thickness, asymetry of drain/source regions caused by nonorthogonal implantation, etc. To systematic mismatches we also including "bad designs", what means layout of cell made without care about it, e.g. different metal coverage of devices, rotating one relate to other, different metal paths resistance seing from source node of transistors, etc.
All of them causing differences in current gain factor and threshold voltages of "theoretical" identical transistors or resistance value for resistors.
We need good matching for precision circuits like D/A and A/D converters or differential amplifiers. For example if You will designing current steering DAC with 8 bit resolution, to obtain INL values below 0.5LSB and then ENOB >7.5bit with 99% of yield your current source for MSB bit should meet following requirement:
\[3 \sigma(I_{MSB}) \leq \frac{100 \%}{2^8} \simeq 0.39 \% \Rightarrow \sigma(I_{MSB}) \leq 0.13 \%\]
The above condition including only statistical effects. Usually we haven't information about gradients of oxide thickness, etc. (sometimes but very rarely its possible to find in process documentation distance matching parameters) so we using special layout techniques to avoid systematic mismatch sources.
For example, for this 8 bit DAC a common/double centroid layout techniques with at least one dummies ring should be used.
For last 32 years peoples wrote many articles and thesis about matching, also a few books seriously discusses this topic.