Why low voltage/low power is difficult to relize in analogIC

Why low voltage/low power circuit is difficult to relize in analog IC design?
However, compared with digital IC disign,they have many methods?

There are lots of reasons. As I know, with low power supply:

(1) the output swing will be limited.
(2): usually, the channel length is short for low powe supply, which will affect the gain.
(3): the SNR is another reason

Re: Why low voltage/low power is difficult to relize in anal

Hi

Most digital elements work in the CMOS tech. the information that is passed is normally a low quantitie of charge and that is it (the actual transfere by writing a "1" is approximately charging a very low F capacitor) - current is almost not invovled in it. Hence - the transistors works in either OFF or in the Saturation - non in the linear zone. The actual bits transfere will be either pulling down a fet-gate, or releasing it - actual current are very very small. Another good mesure to see power consumption in the digital components - the same IC, the higher bit rate - the more power (BIT-RATE = F*Q = more power).
In the analog IC: The main requirement is "LINEAR" - to be in the Active operation mode. that requires, in NPN - Vce>0.2v - most likely about 0.5 - 1v (difficult to get LOW voltages). The other thing - Analog ICs are all about "give me signal, and current". The requirements for S/N ratio (in analog terms) is much more strict than in the digital sense. I am sure you can speculate it more...


Hope it helped

Shutter_man

mainly it is because of the stack of transistors are more difficult and conventional op amp design by cascoding is not working any more.

Re: Why low voltage/low power is difficult to relize in anal

Limitations due to LVLP:
the reduced number of the stacked devices, the reduced linear voltage swing, and the difficulty of turning on the MOS switch over the entire voltage swing.

I think this may be the most concerned according to your question:

The digital world transfers voltage, while the analog transfers power.

Regards.

I think the main reason is the lower supply voltage limits the output swing to be small while the noise level is still the same.
In other words, the Dyanmic Range is small.

Re: Why low voltage/low power is difficult to relize in anal

I agree that output swing is a problem for analog lvlp design.

Many parameter can't match the request: DR SFDR SNR.

Re: Why low voltage/low power is difficult to relize in anal

how to reduce mismatch in analog LSI design

Use common centroid layout method.
Use large size (area) mosfets.
U can read some paper about matching of mosfet.

Re: Why low voltage/low power is difficult to relize in anal

Mismatch could also be reduced my grouping common passive component layout aside with dummy surrounding . Hope this helps

Rgds