Why lockup latch needed for posedge followed by negedge flop

[Varun124]

Hi,
This may be basic question, but want to understand in depth.
1. In DFT, its common to add lockup latch for posedge followed by negedge flop. But since we use slowclock and its shift path, we could still close timing on the shift path. But why still we insert LL.
2. With respect to coverage is there any affect it posses ?
3. Is ATPG tool is not clever enough to understand the half path and generate pattern based on this design ?

Thanks in Advance

 

[dick_freebird]

I think your posedge, negedge is for clock domain
crossing metastability but that really ought to be
solved by applying correct timing, as "a decision"
(anti-metastability) is only sometimes the "right
decision".

If you allow "any decision, as long as it's a decision"
then you have some sort of adaptation needed in
the test program, to determine and deal. Better
than waiting an indefinite amount of time for a
decision, and a semi-infinite field of timing to
"adapt to".

But built in determinism rules for test repeatability.

 

[oratie]

But since we use slowclock

Think about hold (not setup). For case, when scan clock is one and common for all clock domains in your design.

 

[Varun124]

Think about hold (not setup). For case, when scan clock is one and common for all clock domains in your design.

Sorry, could you explain more on this.