Why it cannot be read by Design Compiler? (reading takes too long/stuck)

[KYLI0418]

Why does this verilog program take so long to read in Design Compiler? (It cannot be read normally for several hours)
(No errors or warning messages)
I have changed many versions but they get the same results.
Can anyone help me? QQ
Thanks!

 

[FvM]

What's the target hardware you are trying to synthesize the code for?

A brief look reveals that the large memory blocks used in your code can't be implemented in actual RAM because you reading and writing 30 memory locations in the same clock cycle, would require a 60-port RAM. Even the largest available FPGA won't be able to implement the code. No matter in which compilation phase Design Compiler is presently stuck, it won't produce working logic.

I didn't try to understand the codes purpose. Technically, you are probably able to synthesize the intended function by performing memory access sequentially in a state machine.

 

[ThisIsNotSam]

Here is a hint:

reg [7:0] weight_memory_high [0:269311]

This is more than 2 million flip-flops. And you have at least 2 of those.