Why isn't high side digital output stable?

[jani12]

Our Advanced Drive Assist Systems(ADAS) project is based on Renesas RH850/U2A16 microcontroller. We are using Infineon Technologies TLE75620-EST, SPI Driver for Enhanced Relay Control IC for driving loads. Datasheet is attached. We don't have any loads connected to SPIDER output pins. We're not commanding digital output logic low or logic high. On power up, SPIDER digital outputs pins are not stable. They are toggling between logic high and logic low. Attached is SPIDER OUT0_HS pin unstable waveform measured with oscilloscope.

When we stop code execution, output pin is stable. Please see attached SPIDER OUT0_HS pin stable waveform.

Microcontroller communicates with SPIDER chip over spi interface. Instead of stopping code execution, if we dynamically disable spi communications, would the digital output become stable?

Why is the digital output toggling? Microcontroller is using spi interface for control and diagnosis. Are we sending something over SPI that's commanding the digital output to toggle?

 

[Carry for cents bazar]

Hi jani12,

There can be various reasons. The circuit will help us. Can you please check which module is enabled by default for your MCU at power up. I am guessing your PWM is enabled and used.

From the datasheet:
Two internal PWM Generators for μC offload

page 3:
A serial peripheral interface (SPI) is utilized for control and diagnosis of the loads as well as of the device. Fordirect control and PWM there are two input pins available connected to two outputs by default. Additional ordifferent outputs can be controlled by the same input pins (programmable via SPI).

This should be a software problem of not setting the internal PWM module correctly at the initialization or in the code. Your code seems to activate the module and produce a square wave impulse at the output of the pin.

 

[jani12]

>> A serial peripheral interface (SPI) is utilized for control and diagnosis
Correct! low-level software is writing current to Spider Diag open load register every other 100ms to perform Open Load diagnostics in the Off State. That's why every other cycle, digital output is logic High.