[SOLVED] why is there a delay at my MUX?

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naught

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I think the following code is the combinational circuit, a mux choosing between 3 different sets of data. But the simulation turned out to be different...
could anyone please help with this?

addr6240 is a counter that counts from 0 to 6239. when 0~2079, signal doutb_interleaver_0 is supposed to connect with buffer_data... but there is 1 clock delay...why? in my view, the 2nd "process" is a combinational circuit...

thanks in advance!

Code:
	process(clk,rst)
	begin 
		if(rst = '1') then
			pr_mux <= mux0;
		elsif(clk'event and clk = '1') then
			pr_mux <= nx_mux;
		end if;
	end process;
	
	process(pr_mux, addr6240_delay)
	begin
		case pr_mux is
			when mux0 =>  -- 0 ~ 2079 
				buffer_data <= doutb_interleaver_0;
				if(addr6240_delay = "0100000011111") then  --2079 
					nx_mux <= mux1;
				end if;
			when mux1 =>  --2080 ~ 4159
				buffer_data <= doutb_interleaver_1;
				if(addr6240_delay = "1000000111111") then
					nx_mux <= mux2;
				end if;
			when mux2 => -- 4160 ~ 6239
				buffer_data <= doutb_interleaver_2;
				if(addr6240_delay = "1100001011111") then
					nx_mux <= mux0;
				end if;
		end case;
	end process;

here`s the simulation graph


- - - Updated - - -

I have tried this one, still 1 clock delay.... quite confused...please help...
Code:
	process(addr6240_delay)
	begin
		if(addr6240_delay <= "0100000011111" and addr6240_delay >= "0000000000000") then
			buffer_data <= doutb_interleaver_0;
		elsif(addr6240_delay <= "1000000111111" and addr6240_delay >= "0100000100000") then
			buffer_data <= doutb_interleaver_1;
		elsif(addr6240_delay <= "1100001011111" and addr6240_delay >= "1000001000000") then
			buffer_data <= doutb_interleaver_2;
		end if;
	end process;

- - - Updated - - -

I have added doutb_interleaver_0,doutb_interleaver_1,doutb_interleaver_2 to the sensitive lists of "PROCESS"... and now it works fine...
how strange...I guess if I exclude the doutb_interleaver_1, the "process" might behave like register? or latch... then 1 clock delay is caused.
can anyone give me some explanation....thx in advance...
 
Last edited:

your sensitivity lists do not include all inputs. for example, in the second example "doutb_interleaver_0" is also an input. As the process is written, a change on "doutb_interleaver_0" will not affect buffer_data until addr6240_delay changes. This is particularly evident if addr6240_delay doesn't change every cycle.
 
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    naught

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the addr6240_delay changes every cycle...
in the simulation graph I gave in the 1st post, when doutb_interleaver_0 changes from 0 to 1(if not included in the sensitivity lists, then not affect buffer_data), but the addr6240 also changes from 0 to 1, could you explain a little further, under this condition, why is there still one clock delay?

thanks for your help.
 

add all the required signals to the sensitivity list in the second process, then we can talk.
 
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    naught

    Points: 2
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all the required signals that influences the output shall be included in the sensitivity lists.
I have read this multiple times in the textbooks...thought I had grasped the idea of it...

@permute @TrickyDicky thank you guys all!
 

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