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I think the following code is the combinational circuit, a mux choosing between 3 different sets of data. But the simulation turned out to be different...
could anyone please help with this?
addr6240 is a counter that counts from 0 to 6239. when 0~2079, signal doutb_interleaver_0 is supposed to connect with buffer_data... but there is 1 clock delay...why? in my view, the 2nd "process" is a combinational circuit...
thanks in advance!
here`s the simulation graph
![未命名.jpg 未命名.jpg](https://www.edaboard.com/data/attachments/27/27208-743981158cb40aa57279ba1c714eb62e.jpg)
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I have tried this one, still 1 clock delay.... quite confused...please help...
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I have added doutb_interleaver_0,doutb_interleaver_1,doutb_interleaver_2 to the sensitive lists of "PROCESS"... and now it works fine...
how strange...I guess if I exclude the doutb_interleaver_1, the "process" might behave like register? or latch... then 1 clock delay is caused.
can anyone give me some explanation....thx in advance...
could anyone please help with this?
addr6240 is a counter that counts from 0 to 6239. when 0~2079, signal doutb_interleaver_0 is supposed to connect with buffer_data... but there is 1 clock delay...why? in my view, the 2nd "process" is a combinational circuit...
thanks in advance!
Code:
process(clk,rst)
begin
if(rst = '1') then
pr_mux <= mux0;
elsif(clk'event and clk = '1') then
pr_mux <= nx_mux;
end if;
end process;
process(pr_mux, addr6240_delay)
begin
case pr_mux is
when mux0 => -- 0 ~ 2079
buffer_data <= doutb_interleaver_0;
if(addr6240_delay = "0100000011111") then --2079
nx_mux <= mux1;
end if;
when mux1 => --2080 ~ 4159
buffer_data <= doutb_interleaver_1;
if(addr6240_delay = "1000000111111") then
nx_mux <= mux2;
end if;
when mux2 => -- 4160 ~ 6239
buffer_data <= doutb_interleaver_2;
if(addr6240_delay = "1100001011111") then
nx_mux <= mux0;
end if;
end case;
end process;
here`s the simulation graph
![未命名.jpg 未命名.jpg](https://www.edaboard.com/data/attachments/27/27208-743981158cb40aa57279ba1c714eb62e.jpg)
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I have tried this one, still 1 clock delay.... quite confused...please help...
Code:
process(addr6240_delay)
begin
if(addr6240_delay <= "0100000011111" and addr6240_delay >= "0000000000000") then
buffer_data <= doutb_interleaver_0;
elsif(addr6240_delay <= "1000000111111" and addr6240_delay >= "0100000100000") then
buffer_data <= doutb_interleaver_1;
elsif(addr6240_delay <= "1100001011111" and addr6240_delay >= "1000001000000") then
buffer_data <= doutb_interleaver_2;
end if;
end process;
- - - Updated - - -
I have added doutb_interleaver_0,doutb_interleaver_1,doutb_interleaver_2 to the sensitive lists of "PROCESS"... and now it works fine...
how strange...I guess if I exclude the doutb_interleaver_1, the "process" might behave like register? or latch... then 1 clock delay is caused.
can anyone give me some explanation....thx in advance...
Last edited: