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Why is the Vge waveform of the IGBT like this?(inverter welding machine)

naiv314

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This is a DC inverter welding machine I designed. Now I am facing an issue where the IGBTs are prone to damage when the machine is working under load (with a load). The drive control board uses an SG3525 to output two complementary PWM signals to drive a push-pull circuit, which then goes through an isolation drive transformer to drive the IGBTs on the power board. The attached image shows the Vge waveform of the IGBT (Q1).

[Image description: The oscilloscope screen displays the Vge waveform of IGBT Q1 with measurements and annotations.]

IGBT Vge波形.png
隔离变压器驱动IGBT.png
1111111111111111111111111111.png
22222222222222222222222222.png
 

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This doesn’t look like Miller effect. Miller plateau is at 8-10V

Gate transformer have leakage inductance. With capacitive load there must be an overshoot.

Simple circuit with this effect:

1744279104466.png
Overshoot can be suppressed with RC snubber.
 
Last edited:
This doesn’t look like Miller effect. Miller plateau is at 8-10V
You are right, I overlooked that it's bipolar Vbe with dip around 0. But it's a self-oscillating inverter without much gate signal shaping effort. Thus I guess it's an unavoidable effect of the simple circuit topology.
 
I don't see any obvious issues with the Vge waveform. 10-20% overshoot isn't surprising, especially with a gate drive transformer.

There might be some very high frequency ringing at the peaks of the waveforms, but hard to tell from those scope captures.
 
The "porch" is a Miller signature, shows that gate drive is on the weak side (may be for reasons, and fix may be more, not less "strategic weakness" (if failure is from burnout caused by excess emitter dV/dt induced or transient overvoltage induced phenomena, softer switching backs you off - until it doesn't due to switching losses coming up).

1525 is a voltage mode PwM and has no good way to prevent "flux walk" from any asymmetries in push-pull drive or devices. As you fail at the "big end" this has to be a suspect. What do you see in the primary voltage and current waveforms? Any hint of an increasing imbalance over time that may lead to saturation of the core?

Good bet that a Fine Imported Tool has no better, bigger transformer than a short and hard to access warranty requires and "saturation margin" may lie in either side of nil.
 
This doesn’t look like Miller effect. Miller plateau is at 8-10V

Gate transformer have leakage inductance. With capacitive load there must be an overshoot.

Simple circuit with this effect:

View attachment 198852
Overshoot can be suppressed with RC snubber.
"Okay, I will try according to your suggestion. Thank you."
 
Ah yes - the small oscillation is around the zero crossing of the bi-polar GD waveform - thus:
1744330588405.png

this is a result of the leakage of the GD transformer and the fact that the IC driving the xfmr has a dead time ( both high or low ) - where the IC outputs cannot pull the xfmr to zero volts because of the finite Z ( read leakage L and DC blocking cap and circuit R's ) - hence you get the wee over or under shoot around the zero volts - as the Tx stored energy has to go somewhere,

as long as this does not exceed Vge thres at max device temp - you are OK - other fixes are improved GD circuitry with pnp turn off - or lower leakage GD xfmr with very short leads in the total path and some judicious snubbing across the G-E . . .

I note 4n7 across each G-E - this is likely not helping - even though it slows device turn on - which helps with reduced Vak max on the output diodes.

( some designs just put 560 ohm across each G-E to flatten this - more GD power, 300mW per R - but simple solution )
 
Last edited:
This doesn’t look like Miller effect. Miller plateau is at 8-10V

Gate transformer have leakage inductance. With capacitive load there must be an overshoot.

Simple circuit with this effect:

View attachment 198852
Overshoot can be suppressed with RC snubber.
"In fact, the four CBB capacitors (C9 C9* C19 C19*) I used are 685J 400V, instead of 475J 400V."
 
Ah yes - the small oscillation is around the zero crossing of the bi-polar GD waveform - thus:
View attachment 198860
this is a result of the leakage of the GD transformer and the fact that the IC driving the xfmr has a dead time ( both high or low ) - where the IC outputs cannot pull the xfmr to zero volts because of the finite Z ( read leakage L and DC blocking cap and circuit R's ) - hence you get the wee over or under shoot around the zero volts - as the Tx stored energy has to go somewhere,

as long as this does not exceed Vge thres at max device temp - you are OK - other fixes are improved GD circuitry with pnp turn off - or lower leakage GD xfmr with very short leads in the total path and some judicious snubbing across the G-E . . .

I note 4n7 across each G-E - this is likely not helping - even though it slows device turn on - which helps with reduced Vak max on the output diodes.

( some designs just put 560 ohm across each G-E to flatten this - more GD power, 300mW per R - but simple solution )
"Should a 560R (1206) resistor be connected in series between the gate (g) and the emitter (e)? Is the 4n7 capacitor still necessary?"
 
Ah yes - the small oscillation is around the zero crossing of the bi-polar GD waveform - thus:
View attachment 198860
this is a result of the leakage of the GD transformer and the fact that the IC driving the xfmr has a dead time ( both high or low ) - where the IC outputs cannot pull the xfmr to zero volts because of the finite Z ( read leakage L and DC blocking cap and circuit R's ) - hence you get the wee over or under shoot around the zero volts - as the Tx stored energy has to go somewhere,
这是由于 GD 变压器的漏电以及驱动 xfmr 的 IC 存在死区时间(高电平或低电平)造成的——由于 Z 值有限(读取漏电 L、隔直电容和电路 R),IC 输出无法将 xfmr 拉至零伏——因此,你会在零伏附近得到微小的过冲或欠冲——因为 Tx 存储的能量必须转移到某个地方,

as long as this does not exceed Vge thres at max device temp - you are OK - other fixes are improved GD circuitry with pnp turn off - or lower leakage GD xfmr with very short leads in the total path and some judicious snubbing across the G-E . . .
只要这不超过最高设备温度下的 Vge 阈值 - 那就没问题 - 其他修复方法是改进带有 pnp 关闭的 GD 电路 - 或降低泄漏 GD xfmr,在整个路径中使用非常短的引线,并在 GE 上进行一些明智的缓冲。。。

I note 4n7 across each G-E - this is likely not helping - even though it slows device turn on - which helps with reduced Vak max on the output diodes.
我注意到每个 GE 上都有 4n7 - 这可能没有帮助 - 即使它减慢了设备开启速度 - 这有助于降低输出二极管上的 Vak 最大值。

( some designs just put 560 ohm across each G-E to flatten this - more GD power, 300mW per R - but simple solution )
(有些设计只是在每个 GE 上放置 560 欧姆来使其平坦化 - 更多的 GD 功率,每个 R 300mW - 但解决方案很简单)
like this.png

--- Updated ---

"Should a 560R (1206) resistor be connected in series between the gate (g) and the emitter (e)? Is the 4n7 capacitor still necessary?"
“是否应该在栅极 (g) 和发射极 (e) 之间串联一个 560R (1206) 电阻?4n7 电容是否仍然需要?”
LikeiikeLikeiikeLikeiikeLikeiike.png
 
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Have you considered moving to a 1825 PWM, if this does turn out to be flux walk, saturation, burnout series of events the current mode control might prevent?
 
是的,这个电路确实能工作(当我去掉LM358限流电阻之后) I don't see any obvious issues with the Vge waveform. 10-20% overshoot isn't surprising, especially with a gate drive transformer.

There might be some very high frequency ringing at the peaks of the waveforms, but hard to tell from those scope captures.
 
translated for others:
The problem has been solved. I modified the parameters of the SG3525 chip, adjusted the IGBT model, and replaced it with a high-frequency IGBT. I am currently adjusting the current limiting circuit (LM358 reverse proportional integral current closed-loop control)

I guess this means your GD signal is not a problem.
 


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