T
treez
Guest
Hi,
My consultancy is investigating a 24V, 5A Single FET Offline Flyback for a lighting application which will get used for literally only 4 hours per year. (it’s a LED light which lights the pathway to a Marquee used for Private School Pupils’ parents’ end of year Bash.)
Input voltage is the 390VDC output of a PFC stage.
Operation in BCM
Basic Schematic will be as attached (LTspice sim also attached)
Page 3 of the below (SLUP078) document states that single transistor flybacks need an extra winding so as to achieve non dissipative clamping of the leakage inductance spike. Surely this is not correct?
Also, this document, on page 3, also states that if an RCD clamp is used (with a single transistor flyback) then it will dissipate 15-20% of the output power. Surely this is wildly incorrect?
The attached is a simulation of a 24V, 5A flyback running off Vin=390VDC. The transformer coupling factor is 0.994. The total energy dissipated in the RCDZ clamp is just 2.4W. Is the simulation badly inaccurate about this?
If I reduce the transformer coupling to 0.99, and re-run the simulation I get 3.6W of dissipation in the RCDZ clamp components.
These are vey manageable levels of dissipation.
Also, Some years ago I did a PFC’d single stage , offline, isolated one FET flyback (with a PQ32/20 core) and at 240VAC and 100W input power I was getting significantly less than 740mW of dissipation in the RCD clamp resistor. Also, the efficiency for 100W input power was 90%.......slightly higher than the efficiency I was getting at 60W input power.
So why is the >100W Single FET offline, isolated flyback so badly vilified? Is the attached simulation badly inaccurate in relation to primary clamp losses?
150W Flyback Article (SLUP078)
My consultancy is investigating a 24V, 5A Single FET Offline Flyback for a lighting application which will get used for literally only 4 hours per year. (it’s a LED light which lights the pathway to a Marquee used for Private School Pupils’ parents’ end of year Bash.)
Input voltage is the 390VDC output of a PFC stage.
Operation in BCM
Basic Schematic will be as attached (LTspice sim also attached)
Page 3 of the below (SLUP078) document states that single transistor flybacks need an extra winding so as to achieve non dissipative clamping of the leakage inductance spike. Surely this is not correct?
Also, this document, on page 3, also states that if an RCD clamp is used (with a single transistor flyback) then it will dissipate 15-20% of the output power. Surely this is wildly incorrect?
The attached is a simulation of a 24V, 5A flyback running off Vin=390VDC. The transformer coupling factor is 0.994. The total energy dissipated in the RCDZ clamp is just 2.4W. Is the simulation badly inaccurate about this?
If I reduce the transformer coupling to 0.99, and re-run the simulation I get 3.6W of dissipation in the RCDZ clamp components.
These are vey manageable levels of dissipation.
Also, Some years ago I did a PFC’d single stage , offline, isolated one FET flyback (with a PQ32/20 core) and at 240VAC and 100W input power I was getting significantly less than 740mW of dissipation in the RCD clamp resistor. Also, the efficiency for 100W input power was 90%.......slightly higher than the efficiency I was getting at 60W input power.
So why is the >100W Single FET offline, isolated flyback so badly vilified? Is the attached simulation badly inaccurate in relation to primary clamp losses?
150W Flyback Article (SLUP078)