Why is the NAND gate so hot?

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ALVC family has the lowest output impedance of 25Ω suitable for driving 50 Ohms at low voltage.

All CMOS has Schottkly diode protected inputs for 5mA or around 25 Ohms but if source impedance of over/undervoltage is low impedance from overshoot , impulse or ESD greater than 0.3V then SCR latchup mode is possible resulting in a hot chip shorting out the supply with the internal pnpn substrate structure.

The only fix is to shield all cables and/or use RC filters and/or ferrite donuts to slow down high speed arcs noise nearby.
 
tony_lth said:
my load is 50 Ohm.
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The maximum recommended output current is 24mA. into 50 ohms then the output voltage must be limited somehow to 24mA x 50 ohms= 1.2V. But the output will try to go higher, maybe to 3V then the output current will be 3V/50 ohms= 60mA.

You fried the IC by overloading it.
 
Does it work to replace R56/698 (in post #12) to a ferrite bead, such as 600 ohms?
Or put an inductor between two nand gates?
I want to reduce the overshooting between two gates.
Thanks.
 

Be aware your probe ground length causes overshoot. Eliminate the long leads and only use probe tip & barrel between two pins Sig/gnd

To prevent overshoot load and source impedance should be close.
Recall I said Source Z is ~25 Ohms , adding 25 in series makes source 50 Ohms, Then 100 Ohm pair, pull-up and down makes a matched load.

R56/57/58 is totally mismatched

No to inductor, ferrite bead.
Yes to matched impedance and consider any long interconnects using tight twisted pair or coax.

If you intend to use 50 Ohm to ground then your driver currents are mismatched for high and low but you can still get Vcc/2 swing.
 

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