First of all, why bother using MATLAB to simulate Verilog, when there are tools specifically designed for that task? Once you "make minor syntax changes", all bets are off.
I think you should also look at the updown variable in the simulation. You'll probably see it changing state every other clock.
Verilog is not my native language, but I believe your problem is that you're comparing a reg to an integer. reg doesn't know anything about "sign", so it thinks 0 (counter) is less than xFFFF.