[SOLVED] Why Is my Logical Inverter always Giving Me 'z's?

[kvn0smnsn]

I took my browser to "https://www.edaplayground.com" to run the EDA playground,
and got a display with four windows. In the window on the left I clicked on
(Tools & Simulators) and selected (Synopsys VCS 2021.09). To the right of that
window, on the bottom was a window that output messages; above it was two
windows; in the one on the left I inserted:

// (c) Kevin Simonson 2024

module t_Nt;
reg orig;
wire negated;

Nt nt( negated, orig);

initial
begin
orig = 1'b0;
#2 orig = 1'b1;
#2 orig = 1'b0;
end

always @( negated, orig)
begin
$display
( "time: %2t, negated: %1d, orig: %1d."
, $time , negated , orig );
end

endmodule

and on the right I inserted:

// (c) Kevin Simonson 2024

module Nt ( result, operand);
output result;
input operand;
supply1 power;
supply0 ground;

nmos nm( result, operand, ground);
pmos pm( result, operand, power );

endmodule

Then I clicked on (Run) up at the top, and the window on the bottom gave me the
message:

CPU time: .240 seconds to compile + .318 seconds to elab + .327 seconds to link
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09; Runtime version S-2021.09; Jan 2 11:44 2024
time: 0, negated: z, orig: 0.
time: 2, negated: z, orig: 1.
time: 4, negated: z, orig: 0.
V C S S i m u l a t i o n R e p o r t
Time: 4 ns
CPU Time: 0.600 seconds; Data structure size: 0.0Mb
Tue Jan 2 11:44:17 2024
Done

Why are my values for (negated) each 'z'? Isn't module (Nt) just a logical
inverter? Shouldn't (negated) be '0' when (orig) is '1' and vice versa? What am
I doing wrong?

 

[FvM]

Wrong terminal port of nmos and pmos gates. Control is third not second port.

 

[kvn0smnsn]

Wrong terminal port of nmos and pmos gates. Control is third not second port.

Thanks! That fixed the problem completely.