henryqiu
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// We can also use $random to generate random values for testing
RS1 = 1; RD1 = -100;
RS2 = 2; RD2 = 200;
RD = 3;
`RF_PATH.mem[RS1] = RD1;
`RF_PATH.mem[RS2] = RD2;
SHAMT = 5'd20;
INST_ADDR = 14'h0000;
`IMEM_PATH.mem[INST_ADDR + 0] = {`FNC7_0, RS2, RS1, `FNC_ADD_SUB, 5'd3, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 1] = {`FNC7_1, RS2, RS1, `FNC_ADD_SUB, 5'd4, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 2] = {`FNC7_0, RS2, RS1, `FNC_SLL, 5'd5, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 3] = {`FNC7_0, RS2, RS1, `FNC_SLT, 5'd6, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 4] = {`FNC7_0, RS2, RS1, `FNC_SLTU, 5'd7, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 5] = {`FNC7_0, RS2, RS1, `FNC_XOR, 5'd8, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 6] = {`FNC7_0, RS2, RS1, `FNC_OR, 5'd9, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 7] = {`FNC7_0, RS2, RS1, `FNC_AND, 5'd10, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 8] = {`FNC7_0, RS2, RS1, `FNC_SRL_SRA, 5'd11, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 9] = {`FNC7_1, RS2, RS1, `FNC_SRL_SRA, 5'd12, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 10] = {`FNC7_0, SHAMT, RS1, `FNC_SLL, 5'd13, `OPC_ARI_ITYPE};
`IMEM_PATH.mem[INST_ADDR + 11] = {`FNC7_0, SHAMT, RS1, `FNC_SRL_SRA, 5'd14, `OPC_ARI_ITYPE};
`IMEM_PATH.mem[INST_ADDR + 12] = {`FNC7_1, SHAMT, RS1, `FNC_SRL_SRA, 5'd15, `OPC_ARI_ITYPE};
reset_cpu();
check_result_rf(5'd3, 32'h00000064, "R-Type ADD");
check_result_rf(5'd4, 32'hfffffed4, "R-Type SUB");
check_result_rf(5'd5, 32'hffff9c00, "R-Type SLL");
check_result_rf(5'd6, 32'h1, "R-Type SLT");
check_result_rf(5'd7, 32'h0, "R-Type SLTU");
check_result_rf(5'd8, 32'hffffff54, "R-Type XOR");
check_result_rf(5'd9, 32'hffffffdc, "R-Type OR");
check_result_rf(5'd10, 32'h00000088, "R-Type AND");
check_result_rf(5'd11, 32'h00ffffff, "R-Type SRL");
check_result_rf(5'd12, 32'hffffffff, "R-Type SRA");
check_result_rf(5'd13, 32'hf9c00000, "R-Type SLLI");
check_result_rf(5'd14, 32'h00000fff, "R-Type SRLI");
check_result_rf(5'd15, 32'hffffffff, "R-Type SRAI");
Everytime I run the testbench the first instruction works well but afterwards, the instructions stop loading for some reason. They are all manually written in by how the testbench works
RS1 = 1; RD1 = -100;
RS2 = 2; RD2 = 200;
RD = 3;
`RF_PATH.mem[RS1] = RD1;
`RF_PATH.mem[RS2] = RD2;
SHAMT = 5'd20;
INST_ADDR = 14'h0000;
`IMEM_PATH.mem[INST_ADDR + 0] = {`FNC7_0, RS2, RS1, `FNC_ADD_SUB, 5'd3, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 1] = {`FNC7_1, RS2, RS1, `FNC_ADD_SUB, 5'd4, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 2] = {`FNC7_0, RS2, RS1, `FNC_SLL, 5'd5, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 3] = {`FNC7_0, RS2, RS1, `FNC_SLT, 5'd6, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 4] = {`FNC7_0, RS2, RS1, `FNC_SLTU, 5'd7, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 5] = {`FNC7_0, RS2, RS1, `FNC_XOR, 5'd8, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 6] = {`FNC7_0, RS2, RS1, `FNC_OR, 5'd9, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 7] = {`FNC7_0, RS2, RS1, `FNC_AND, 5'd10, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 8] = {`FNC7_0, RS2, RS1, `FNC_SRL_SRA, 5'd11, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 9] = {`FNC7_1, RS2, RS1, `FNC_SRL_SRA, 5'd12, `OPC_ARI_RTYPE};
`IMEM_PATH.mem[INST_ADDR + 10] = {`FNC7_0, SHAMT, RS1, `FNC_SLL, 5'd13, `OPC_ARI_ITYPE};
`IMEM_PATH.mem[INST_ADDR + 11] = {`FNC7_0, SHAMT, RS1, `FNC_SRL_SRA, 5'd14, `OPC_ARI_ITYPE};
`IMEM_PATH.mem[INST_ADDR + 12] = {`FNC7_1, SHAMT, RS1, `FNC_SRL_SRA, 5'd15, `OPC_ARI_ITYPE};
reset_cpu();
check_result_rf(5'd3, 32'h00000064, "R-Type ADD");
check_result_rf(5'd4, 32'hfffffed4, "R-Type SUB");
check_result_rf(5'd5, 32'hffff9c00, "R-Type SLL");
check_result_rf(5'd6, 32'h1, "R-Type SLT");
check_result_rf(5'd7, 32'h0, "R-Type SLTU");
check_result_rf(5'd8, 32'hffffff54, "R-Type XOR");
check_result_rf(5'd9, 32'hffffffdc, "R-Type OR");
check_result_rf(5'd10, 32'h00000088, "R-Type AND");
check_result_rf(5'd11, 32'h00ffffff, "R-Type SRL");
check_result_rf(5'd12, 32'hffffffff, "R-Type SRA");
check_result_rf(5'd13, 32'hf9c00000, "R-Type SLLI");
check_result_rf(5'd14, 32'h00000fff, "R-Type SRLI");
check_result_rf(5'd15, 32'hffffffff, "R-Type SRAI");
Everytime I run the testbench the first instruction works well but afterwards, the instructions stop loading for some reason. They are all manually written in by how the testbench works