Why is Flyback loop compensation made so opaque

[cupoftea]

Hi,
An investigation of Current mode, offline, Flyback chips and their App notes shows none do the feedback loop calculation well.
All that needs to be done, ayk, is to convert the flyback into the equivalent buckboost, and then apply the buckboost equation (whuich is seen in the below app note by microsemi)

For example, the attached LTspice is an np/ns = 84/19 flyback, with vout = 24v and vin = 88V.
Fsw = 65khz.
When converted to buckboost, the vin becomes some 19v, since the duty cycle must be same.

Refer things to sec side, since the sec side has any post LC filter. So just make the Rsense = Rsense * (ns/np)^2.

Flyback feedback loop equations: (page 9)

https://www.microsemi.com/document-portal/doc_view/124786-voltage-mode-current-mode-and-hysteretic-control#:~:text=In%20classic%20voltage%20mode%20control,applied%20to%20the%20PWM%20comparator.

Its Not even worth applying the transfer function that includes the slope compensation, since it wont affect the crossover frequency anyway. Without the slope, the transfer function bode plot will show the peaking due to the sub harmonic oscillation, but this is at approx Fsw/2…well above your crossover frequency. You will of course, if necessary, apply slope compensation as per downslope/2, or a little less, if your max duty cycle is just 0.55, say.

Page 10 of the following shows how to get the overall transfer function when you also have a post LC filter..
*..Practical feedback loop considerations for switch mode power supplies:

https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwjayN2fjsWBAxXRQkEAHSFlBX8QFnoECBoQAQ&url=https%3A%2F%2Fwww.researchgate.net%2Fprofile%2FMohamed-Mourad-Lafifi%2Fpost%2FHello_it_is_a_power_system_stabilizer_How_to_calculate_the_gain_margin_in_the_bode_plot_if_the_phase_is_always_above_the_0_degree%2Fattachment%2F59d635f479197b80779936c8%2FAS%253A386285110874112%25401469108955496%2Fdownload%2FPractical-Feedback-Loop-Design-Considerations-for-Switched-Mode-Power-Supplies.pdf&usg=AOvVaw1nV06ZJ6OWyxExmMFKNo_H&opi=89978449

--- Updated Sep 25, 2023 ---

Why do the semicos not cover this subject well?

 

[D.A.(Tony)Stewart]

Classic closed loops must be 1st order at the crossover at zero Av or deg. SMPS feedback is best design to look like a 1st order loop at the 0 dB or deg loop crossover. So various techniques are used along with PFM , current and voltage feedback to operate over the entire range of loads. Look up Chris Basso's presentation or books for the best advice.

 

[cupoftea]

Thanks...

Do you agree, page 6 of the document “Practical Feedback Loop Design considerations for switch mode power supplies” is in error?

Practical Feedback Loop....

…..I am referring to equation (18) of page 6, ie, the value “Km = delta IDSpk/delta VEA”.
This “Km” value occurs in the Power stage transfer function of the BuckBoost in equation (21) of the same page.

However, the equation (18) is nonsense. So too is the diagram below it in figure (10).
The “Modulation Gain” that’s being referred to should actually be “R/Ri”

Where:
R = Load resistance
Ri = Current sense resistor in source of FET.

There is usually another gain associated with the modulator (actually an attenuation), which is the factor by which the “VEA” error amplifier output voltage is divided down before it is taken into the PWM comparator. Usually a factor of 0.25 or so. However, the page does not actually mention this.

The document TN-203...(at the bottom of page 9, for buckboost...)
“Voltage mode, current mode (and hysteretic control)”, as follows
https://www.microsemi.com/document-...tage-mode-current-mode-and-hysteretic-control

..Gets the Modulation gain correct, they however, for whatever reason, call the Sense resistor, the “RMAP” …ie, the “PWM ramp voltage divided by the ramp current”…….this is Ohms Law, and is in fact the sense resistance , Ri.

However, they unfortunately don’t make any reference to the gain (attenuation) involving the dividing down of the error amplifier output voltage.

Do you know why none of these papers can “call a spade a spade”?

 

[dick_freebird]

Semiconductor companies would prefer you not just take
their app note and make a board out of it. They always
disclaim the hell out of anything they publish. And if the
app note was written by anyone who ever designed a power
supply, that would be a bit of luck (some companies' customers
seem to be luckier than others). Often applications engineers
are drawn from other engineering roles if they have decent
"customer-facing" qualities, but that pool is semiconductors,
not power supplies.

Unless your company sees applications engineering as
"pre-sales" customer enablement rather than "post-sales"
customer mollification. But that would be forward-thinking.

 

[D.A.(Tony)Stewart]

Thanks...

Do you agree, page 6 of the document “Practical Feedback Loop Design considerations for switch mode power supplies” is in error?

NO.

However, the equation (18) is nonsense. So too is the diagram below it in figure (10).
The “Modulation Gain” that’s being referred to should actually be “R/Ri”

NO it is a current mode modulator block, not a voltage regulator.

 

[cupoftea]

Thanks, they have omitted the inevtable scaling factor that is used to scale the VEA, the error amplifier output voltage...this is an important feedback loop parameter, i believe you would agree.