Why is 28 Transistor CMOS Design widely used in the industry?

[mgowda45]

I am a student trying to understand

1.)why 28 Transistor CMOS design used everywhere?

2.) why isn’t TSPC Register used instead of MUX based flip flop?

 

[crutschow]

why 28 Transistor CMOS design used everywhere?

Where is "everywhere"?
What is the circuit?

 

[mgowda45]

I mean the conventional 28T Adder design.


The conventional flip flop design is attached below,



The TSPC D Flipflop design,



Thank you,
mgowda45

 

[dick_freebird]

28nm is just about fully bottomed out in cost, finer nodes
still have yield learning to do and more expensive equipment
yet to amortize. And as you go shorter-channel, analog keeps
getting crappier. Like I saw op amps in GF14 which had AVOL
of 40dB or slightly less, and the outfit that did them was all
happy about that. Looked like junk to me.

There's a lot for which non-leading/bleeding edge technology
can be used. Sometimes you're better off.

 

[BigBoss]

Why because, a nice article.

The importance of ensuring supply for foundational semiconductor chips

Why 45- to 130-nanometer process nodes matter

news.ti.com

 

[D.A.(Tony)Stewart]

The TSPC design has no dual CLK with shorter setup time with fewer transistors.

--- Updated Mar 31, 2024 ---

Is the 28T adder used everywhere ? Or just as a lowest power 3 bit adder.

https://www.researchgate.net/publication/221381046_Ultra_Low_Power_Full_Adder_Topologies/figures?lo=1

 

[dick_freebird]

Is the TSPC 'flop the same as the "dynamic DFF"? Sure
looks similar. Seen them used in prescalers where a regular
'flop won't self-toggle fast enough. Real easy to upset them
if you're -not- running fast, though. There is no positive
feedback storage mechanism, just parasitics holding charge
they were or weren't given. For a while.

US6737900B1

 

[D.A.(Tony)Stewart]

TSPC true single phase clocks were patented in ‘96. They are simpler and thus use less dynamic power and faster than the Transmission gate version used in the CD4000 era.

 

[glennramalho]

There are other issues with dynamic flops and there are other similar designs. The main one is they eventually loose the data. So you need to constantly refresh or change the value.

So the standard flop is easy to use, well understood, you can stop the clock and it will hold the data as long as there is energy, and you will save power. So for the vast majority of designs this will do fine. It is also easy to build as a standard cell so it fits well with the synthesis and P&R flows as well as the DFT scan chain flow.

Now, there are places where time is critical and you might use another approach. I worked several years ago for a DRAM maker and there they would use dynamic FFs on the data path. The reason is they needed the speed, so the traditional flop did not do it, and they did not care if the data was lost as they knew the CPU caught the data immediately and the value was soon replace with another. But it should be mentioned that the timing has to be careful and the layout was then full custom. So it is a lot of effort to do it, so it is basically built by hand as you would any analog circuit. Then there will be a functional test flow just for checking this guy.

So, the traditional flop is everywhere because it is simple, but when needed one can use something else built by hand.

 

[D.A.(Tony)Stewart]

TSPC or "True Single Phased Clock" FFs have many variations in number and size of transistors.
The minimum number is 5 transistors yet these consume much more power than the larger area more transistor versions.

So the main tradeoff is chip complexity +size vs. power efficiency and as speed performance variations.

The conventional design used in CD4xxx series used TG (transmission gate) dual CLK phase technology with higher impedance, lower current and lower speed.

https://www.ijrte.org/wp-content/uploads/papers/v8i1/A1382058119.pdf