Why increase transistor area will decrease flicker noise?

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thomasy

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Flicker noise is generated by trapping of carrier beneath oxide layer, but how it comes if we increase the area of transistor can reduce flicker noise?
Can someone answer this question?
One explanation is saying statistically it's lesser trapping, but I didn't see it's a reasonable one.
 

... how it comes if we increase the area of transistor can reduce flicker noise?

This is only valid for constant drain current, and under sole consideration of the carrier density fluctuation (McWhorter) model, i.e. not considering other models like the mobility fluctuation (Hooge) or the charge trapping and de-trapping near the Si–SiO2 interface process mentioned by you. BSIM MOS models include all these flicker noise processes, and - depending on process management and control, i.e. the main model contributors - this McWhorter 1/WL dependency may be valid or not.

See e.g. Binkley: Tradeoffs and Optimization in Analog CMOS Design, chap. 3.10.3 Flicker Noise :
 

You detrap one carrier, you get q charge collected on C
for a voltage step of q/C. Double area, double C, same q.
Tricky, huh?
 

You detrap one carrier, you get q charge collected on C
for a voltage step of q/C. Double area, double C, same q.
Tricky, huh?

Nice explanation! But why wouldn't you detrap more q charges, as interface trap density ~ area?
Is the trapping/detrapping process much more proportional to the current density below the interface?
 

The trap / detrap process is very long timescale. So the areal
effect on trapping would be frequency (still lowish, still random)
and not the amplitude of any individual event. I think the
probability of time-coincident detraps is very very low.

I'd say area moves the voltage amplitude down, and the
frequency axis to the right (which would move the amplitude
up slightly), but I think source amplitude (q/C) has more
effect on observed noise voltage (which tends to be dealt
with in detail-obscured, rms type terms).
 

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