hi
can any one clear me this problem related wth verilog?
for the folowing stmt
always@(posedge clk or negedge reset)
.
.
.
endmodule
// i am getting the code simulated correctely but NOT synthesisable..
when i change the stmt always@(posedge clk or posedge reset)
it gets synthesised
y i am not getting synthesised i mix rising and falling edge.?
what is the reason?
You might want to check your target library to see if a async reset (active low) DFF exists. Check your synthesis log file carefully, it will tell you why it's not synthesizable.
This is not due to always statement but may be due to one of the statements inside of this block!
check ur code and tell me , have u made any mistake like checking reset == 1 instead of reset==0
In your code it is very much necessary to have active low reset ( u are checking negedge of reset) ... that is asynchronus active low reset. If this is the case then may be u are using a very old tool. which tries to map posedge / negedge to flipflop .. some tools used to do this! . To remove this simply remove the negedge for reset and have something like
always @(posedge clk or reset) .
this wlll solve the problem
hi friends
thanks for ur replies.
i had written as
1)always@(posedge clk or negedge reset)
if(reset) // this was the mistake.
<statements>
when i changed the condition to
2)if(reset ==0)
<statements>
the code gets synthesised.
but is this the problem related with tool??
the same can be tried with the code given for Dff given by Mr.Nand_gates.
the synthesis tool i use is xilinx 6.3.03i and leospec.guys if u r using any latest verson of these tool, plz check it.
regards
hari
always @ (posedge clk or negedge reset)
if (reset)
q <= 0;
...
This means this always block is to be executed on positive edge clock & the reset is ??
from sensitivity lest it is active low but from ur condition it is active high so it is not synthesiable.
ur solution is correct.
Hint: Read The HDL manual of ur synthesizer before using it. you will find code examples for most of blocks u want to describe.
Regards,
Amraldo