Why has such a big ground plane been used in this switch mode buck led driver?

The following ZXLD1370 Buck LED driver evaluation board document shows the schematic on page 2 and the PCB layout (top and bottom layers) on page 6.

ZXLD1370 Evalution board (switch mode buck led driver)
**broken link removed**

Note how the ground plane on the bottom layer extends completely underneath the power inductor, L1.
Why did they not make the ground plane less extensive and instead use some of the bottom layer area beneath the power inductor as thermal spreading copper for the inductor? (they could have used thermal vias to conduct heat down to the bottom copper layer from the inductor).

I am speaking about the “LEDK” net, to which one pad of the power inductor is connected…….ie, why isn’t the “LEDK” net used on the bottom layer, as spreading copper for the power inductor?

Aren’t they just blindly putting in a ground plane for no reason? Obviously a certain amount of ground plane is suitable for the control ground, but not the huge ground area seen on the bottom layer of page 6. Why have they used such a big extensive ground plane?

The principles of laying out this kind of switching supply, are
1…Make all switching power current loops as narrow in area_contained as possible
2…..Do not run power switching currents through lengths of control ground.


…none of the above requirements calls for an extensive ground plane in such a buck led driver as this…..so why have they used such an extensive ground plane?…after all, the copper area used for ground could have been used for thermal spreading copper for the power components (FET, diode and inductor).

You are missing one of the other considerations: it is cheaper to produce boards when less copper has to be etched from them. All other things being equal, the less copper you etch away, the cheaper the etching process becomes because the solvent chemicals lasts longer.

Brian.

yes true, but I too would keep the copper, just make it copper that's connected to a power component so it acts as thermal copper to improve thermal situation and reduce component heating.......as you know the diode and inductor have no connection to ground....the mosfet drain (heat pad) is not connected to ground...as you know , ground is not good for thermal copper useage in this case

I am sure you will agree that Switch mode supplies tend to need "star-grounding", and not just mindless use of a large overall, all-covering ground plane?

Putting a ground plane there will likely provide significant screening of the EMI coming from the switching node. Connecting the plane to the power components would only make EMI worse. Thermal conductivity improvements would probably be modest, unless you put a huge number of vias in there. And depending on how the board is mounted it might not matter at all.

The layout diagram of page 6 (bottom layer) of the document linked in the top post shows that they have actually brought the switching node out on the bottom layer with thermal vias to it (the six thermal vias near the mosfet drain). The switching node also has a fairly significant copper pour on the top side.
In any case , the LEDK node could also have been used to screen the switching node, since as far as high frequencies are concerned, its only separated from the power rail (VIN) by the output capacitors, which high frequencies would see as a very low impedance.
Also, the bit of the ground plane below the LEDK pad of the inductor is not beneath the switching node, and so would not be screening it.
I have read many datasheets which tell not to put pieces of ground plane beneath the switching node as it would have noise coupled into it.
The power inductor has 9 amps flowing in it , and surely the priority is too cool it down, by adding a significant as possible amount of thermal spreading copper, and thermal vias to bottom layer cooling copper.
This is a surface mount inductor, and the main method of cooling for it is via the board copper, so I am surprised to hear that board copper is not being regarded as having a significant cooling effect for it. Thermal vias to bottom layer copper are an accepted heat conduction method for surface mount components..surely?

Also, I am sure you will agree with the following?...
Please observe the size of the power switch loop...from C3 vin pad....then through R1 and R2, then through C3 and C5, then all the way round to L1's LEDK pad, then through fet drain...source...and back to C3 again..........
..that is a loop with a very unecesarily wide area. Surely you agree?
In fact, its about as wide as it could be on that size of board...very poor layout?

Also, I am sure you will agree with the following?...
Please observe the size of the power switch loop...from C3 vin pad....then through R1 and R2, then through C3 and C5, then all the way round to L1's LEDK pad, then through fet drain...source...and back to C3 again..........
..that is a loop with a very unecesarily wide area. Surely you agree?
In fact, its about as wide as it could be on that size of board...very poor layout?

Click to expand...

Essentially not. The switching loop is through C3/C4/C11/C12, Q1 and D1.
L1, LED and R1/R2 carry constant current in a first order.

But anyway, the evaluation board isn't advertised as a design guide. There's a separate application note "ZXLD1370 PCB Layout Guidelines".

By the "power switch loop", I mean the loop of current that flows through the fet when the fet is on.
-I am sure you will agree that this loop doesn't comprise the power diode, D1. The diode is in the "rectifier loop", as I appreciate you are cognisant.
The inductor current, I am sure you will agree, is triangular, and thus has regular discontinuities where there is a very high di/dt, since the current changes very very quickly at the peaks and troughs.
I do agree that the inductor current is less discontinuous than the fet current or the diode current, which carry trapezoid pulses.
When I said "C3" I meant all of the input capacitors, but just put "C3" for brevity.

I am sure all agree that the power switch loop and the rectifier loop need to be as narrow in area as possible.

Also, the inductor does carry 9 amps, and is surface mount, shielded and is worthy of a lot more thermal copper than they've given it....but as I often find in the work of contractors who come to us, they shovel in ground planes as if its the be-all-and-end all and forget about thermal copper.

Here is the article on layout:-
**broken link removed**

..its quite right of them to point out the traces with highly discontinuous current in them, and the main problem with this is the danger of the ground in between the source of the fet and the cin snaking around the control ground......but they have avoided that.
With discontinuos current traces and radiated emissions, it is the loops of current that radiate, so to reduce radiation, one reduces the area of the current loops. The two current loops at play here are the fet loop and the rectifier loop.

The app note recommends ample use of thermal copper, but in their example they failed to do this, due to overuse of a too-big ground plane area....again, its something we've seen from contractors time and time again........we even saw a 40W buck led driver with no thermal copper whatsoever, and fet diode and inductor on minimal pads, and all of the top and bottom layers around them being ground copper fill...none of the fet, diode or inductor had a connection to the ground. This company still trade, and have a fancy website, and they argued with us that no thermal copper was needed , just their huge ground plane, to reduce EMC problems..

Components that are both in the "transistor" and "diode" current path (L1, LED and R1/R2) carry essentially constant (or more exactly only continuously variable) current. Their wiring doesn't induce much voltage and isn't critical.

The components with critical placement are also identified in the said ZXLD1370 PCB Layout Guidelines (figure 2 for buck converter topology).

treez said:

The following ZXLD1370 Buck LED driver evaluation board document shows the schematic on page 2 and the PCB layout (top and bottom layers) on page 6.

ZXLD1370 Evalution board (switch mode buck led driver)
**broken link removed**

Note how the ground plane on the bottom layer extends completely underneath the power inductor, L1.
Why did they not make the ground plane less extensive and instead use some of the bottom layer area beneath the power inductor as thermal spreading copper for the inductor? (they could have used thermal vias to conduct heat down to the bottom copper layer from the inductor).

I am speaking about the “LEDK” net, to which one pad of the power inductor is connected…….ie, why isn’t the “LEDK” net used on the bottom layer, as spreading copper for the power inductor?

Aren’t they just blindly putting in a ground plane for no reason? Obviously a certain amount of ground plane is suitable for the control ground, but not the huge ground area seen on the bottom layer of page 6. Why have they used such a big extensive ground plane?

The principles of laying out this kind of switching supply, are
1…Make all switching power current loops as narrow in area_contained as possible
2…..Do not run power switching currents through lengths of control ground.


…none of the above requirements calls for an extensive ground plane in such a buck led driver as this…..so why have they used such an extensive ground plane?…after all, the copper area used for ground could have been used for thermal spreading copper for the power components (FET, diode and inductor).

Click to expand...

The layout focuses on thermal emission for the top layer and EMI absorption for the bottom ground layer. The hotspot will most likely be the Power LED. The current shunt (2large SMD R's) path to Vcc bypasses the top layer and goes direct to Vcc on the bottom layer to avoid the diode surge current drop on the top area. While a single point ground reference is maintained near the gnd. input with a few micro vias.

The Loop current area is large but flattened by the effective bottom ground plane. It looks like a reasonable layout but not thermally optimum for the LED, which is why thermal feedback is employed. For something of this power density, MCPCB would be required. Large top area conductor loss is low inductance. Inductor losses can be calculated from coil R but are likely to be small compared the LED drop.

thankyou for looking at it, I appreciate your time, though I know that if you looked more deeply into this you would have seen that the presence of the ground plane bit on the bottom layer doesn't "flatten" out the power switch loop. There are no leds mounted on this pcb.
The only bit of ground through which power switching current flows as that little bit of ground inbetween the source of the fet and the input capacitors. -this is , or would be known as, the star point.
No power switching current flows through the majority of that bottom layer ground area.