I am designing an op amp with folded cascode input stage , and a push pull common source output stage. But after hands on calculation, i run spice simulation, and the result showes minus gain value.
What's the problem might be?
You need to check the operating regions of the transistors ( be sure they are all region 2 )
If this is OK, then I think you need a closed loop simulation ( perhaps using stability analysis "stb" in Cadence ). The class AB output stage is most probably unstable ( you cannot guarantee both N and P MOS are in saturation in quiescent mode, due to current mismatc between the two )
when i check the DC operating point, found the out voltage was driven to close Vcc(4.4V), and some transistor in the circuit seems out of saturation region.
I think i should re-decide the W/L ratio of the transistors.
hi, fendy
Thanks for your advice.
For the low voltage current source, Vg(M7, M9)=Vth+Von, (where Von=Vgs-Vth), and Min. Vg(M6,M8)=Vgs6+Von7=Vth+Von6+Von7=Vth+2Von(cause W6/L6=W7/L7=W8/L8=W9/L9).
So the voltage drop on the resistor R0 is Von, set your Von ( for example, 0.25V) and calculate R0 by current. Then calculate W/L of M6,7,8,9. The voltage on the drain of M8 can be as low as 2Von, which is 0.5V.