Why filler cells prevents LATCH UP?

In my chip layout I got a DRC error stating LATCH UP; but after inserting the filler cells I didn't get a DRC error due to LATCH UP;
So please tell me how filler cells prevents LATCH UP (as it is an empty cell without any function)

The filler cell are required to have a continuous n-well between each std cell, and certainly fix this latch-up DRC.

rca said:

The filler cell are required to have a continuous n-well between each std cell, and certainly fix this latch-up DRC.

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How continuous n-well helps in preventing latch-up; please explain-> the relation between continuous n-well & latch-up

Hi

Filler cells are used only for continuity of well .
Imagine there are two standard cells with some space left in between them. so there is a discontinuity in the NWELL (for a NWELL bulk process) in this empty space, which affects your lithography step. In order avoid this, designer should make sure that there is no discontinuity in the NWELL by placing a filler cell.(Which fills the NWELL)
Also, there could be some mechanical stress by the layers present above the vacant space

Latch up:

Forming the npn or pnp transistors inside CMOS called Latch up. In olden days with help of Guard Rings we are preventing Latch up. These Guard Rings are present inside the CMOS. So it directly impacting area. Even to avoid that area issue nowadays we are using some TAPcells to prevent the latchup. As for fab rules we are keeping TAPcells to some specific distance to avoid latch up