Well, I use the "+" symbol in my RTL for addition and XOR in CRCs as they are functionally correct. I then feed the RTL to a synthesiser which is free to use functionally equivalent logic to implement the design in the best time/area tradeoff according to my constraints. If it uses XORs in a final netlist, it will be becuase they are best for that situation.
Because XOR gate gives you a half adder. You just add the carry-bit computation to implement a full adder, which can be extended to whatever bit-size you want.
SUM = A xor B xor CIN
COUT = A.B + A.CIN + B.CIN