Digital Design and Embedded Programming
PLD, SPLD, GAL, CPLD, FPGA Design
Why Does Verilog Remember Number of Bits from one Input Parameter to the Next?

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[QUOTE="FvM, post: 1788777, member: 152255"] According to Verilog language reference manual, ports abc and def share the preceeding range definition. Everything works as expected. [/QUOTE]

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Digital Design and Embedded Programming
PLD, SPLD, GAL, CPLD, FPGA Design
Why Does Verilog Remember Number of Bits from one Input Parameter to the Next?

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