[SOLVED] Why Does Verilog Remember Number of Bits from one Input Parameter to the Next?

[kvnsmnsn]

I had a question about how Verilog works, so I built a dummy design and its testbench as follows. The design is:

// (c) Kevin Simonson 2025

module lfRg ( output        rslt
            ,  input [ 2:0] abc
            ,               def);

  assign rslt = abc[ 0] == def[ 0] & abc[ 1] == def[ 1] & abc[ 2] == def[ 2];
endmodule

and the testbench is:

// (c) Kevin Simonson 2025

module t_lfRg;
  reg  [ 2:0] abc;
  reg  [ 2:0] def;
  wire        rslt;

  lfRg lr( rslt, abc, def);

  initial
  begin
       abc = 3'b000; def = 3'b000;
    #3               def = 3'b001;
    #3 abc = 3'b001;
    #3               def = 3'b010;
    #3 abc = 3'b010;
    #3 $finish;
  end

  always @( rslt, abc, def)
  begin
    $display
      ( "t: %2t, rs: %1b, ab: %3b, de: %3b"
      , $time  , rslt   , abc    , def);
  end
endmodule

I didn't expect this to compile, because it certainly looks to me like module (lfRg) has input value (def) of one bit, and (t_lfRg) treats it like it's three bits. But when I put this into EDA Playground ("https://www.edaplayground.com"), it works just fine; it compares (3'b010) with (3'b010) and returns a (1), just as if (lfRg)'s (def) was expected to be three bits. Does Verilog treat an input parameter as if it has the same number of bits as the input parameter before it, even though I didn't explicitly list the ([ 2:0]) for (def)?

But perhaps more to the point, if that answer is yes, and if I've declared an input parameter to be three bits long, how do I then specify after that an input parameter that is only one bit long?

 

[FvM]

According to Verilog language reference manual, ports abc and def share the preceeding range definition. Everything works as expected.

 

[FvM]

For clarity, I'd format the module interface definition so:

---

Code Verilog - [expand]
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module lfRg ( 
    output      rslt,
    input [2:0] abc, def
);

---

 

[pbernardi]

if you want "def" to be declares as one bit, try:

---

Code Verilog - [expand]
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module lfRg ( output        rslt
            ,  input [ 2:0] abc
            ,  input        def);

---

Otherwise, you declaration becomes (I just removed the newline and some spaces):

---

Code Verilog - [expand]
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module lfRg ( output        rslt
            ,  input [ 2:0] abc, def);

---

So you are atributting [2:0] to both "abc" and "def".