Look in THE ART OF ELECTRONICS on pag 242 until 248. In forum has the book for download ... the circuit when you work with a buffer is very nerly of 180º margin, if you add a RC network on output you elimine the internal frequency compesation of aomp. Then aomp osc... you have to create a dominante pole for eliminate this effect.
I think there is some problem with ur circuit regarding phase margin. The phase plot which u have given is not showing dominant pole characteristic rather it is not the actual characteristic which u should get from ur design.u should keep the phase margin more than 60 degree to get the thing stabilize.have u checked ur circuit with out any output stage if yes then tell me what was the gain and phage margin u r getting from there.
can you tell me how can i find this book?
i looked for this book in the forum,but i couldn't find it.
leomecma said:
Look in THE ART OF ELECTRONICS on pag 242 until 248. In forum has the book for download ... the circuit when you work with a buffer is very nerly of 180º margin, if you add a RC network on output you elimine the internal frequency compesation of aomp. Then aomp osc... you have to create a dominante pole for eliminate this effect.
For the plot I have given, the phase is not right.
I changed the structure of the class-AB output stage, and modified the compensation capacitor.
Now, it's ok.