why does latches save power

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nick_yang

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I'm read that a latch based design can save power because latches are level sensitive and don't need a clk, I don't think this is right because in a two phase latch design latches still need clk to trigger even though it's level sensitive. could someone explain it for me?
 

Every time a signal (clk) changes state, current is required to charge parasitic capacitances (I=C*dv/dt). If there's no change in signal level, no current is drawn. This is called dynamic current, as opposed to static, or idle, current. A clock is continuous, a latch control is not.
 
FF : Two latches...so the flop has bigger area which means more clock parasitics so on a cell level you have bigger power. So the choice between latches and FF's is based on the timing methodology at the chip level. So the choice of FF vs latch depends on the methodology for timing closure.
The latch timing analysis is much more complex compared to FFs. It requires a lot of customization while FF's are very tool friendly. THIS IS A BIG DEAL.
 

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