I want to know more about this golden model stuff.. I know that when hardware spec is available, first thing to be done is to write a golden model for it in C/C++. What I am not sure about is why we have to this?? Why can we not write the verilog code for design directly????
The idea is that it's easier to write a functionally correct model at a higher level abstration, such as in C/C++. This then gives you something to verify the HDL against. It's not a good idea in all cases and quite often, HDL will be coded and verified on its own.