Why do we put a Latch at the output of AD converter?

[zahrein]

Guyz,

I am designing FLASH type AD converter.Just wondering why we shoud put a LATCH at the output. IN this case, i put a D FLIP FLOP.

Here i attach the schematics.

 

[Vamsi Mocherla]

Normally Latch is a storage device.It holds to the data till the next clock phase. In the case of Flash A/D, the input is not sampled. Hence if the input is changing too fast, then the output will have to respond. The next block may not be ready for this. So, we hold on to the data till the next clock phase. This will ensure that the data is consistent with respect to the clock.

 

[lucky8]

what is (are) the difference between latch and flip-flop?

 

[zahrein]

The latch is general term...Latch can have D flip flop- sr flip flop...Latch is a logic gate!!!

Do read book before u ask?

 

[rogerliu]

what is (are) the difference between latch and flip-flop?

The Flip-Flop is consist of a master latch and a slave latch, the enable pin of these two latch is invert, so the Q of the Flip-Flop is changed when clock rising or falling

 

[tuza2000]

Is output buffer necessary in flash adc design?
if necessary,how can i design it with right size?
thx

 

[sunking]

Is output buffer necessary in flash adc design?
if necessary,how can i design it with right size?
thx

it is necessary.
the size you can use as that of digital Lib

 

[ocarnu]

The latch does what the D FF does, you don't want data changing at the output ranndomly.
The buffer is simply sized depending on the capacitive load expected. Pins + PCB routing + next chip or whatever you put there (logic analyzer probe). You should be abble to reach a logic level in one clk period.

 

[tuza2000]

is it necessary package in order to test the adc chip?
how to chose the means of pacakging?
how to know the size of the capacitance load?
what kind of instrument that i need to test the chip?
i heard that it is hard to test an adc chip
i am designing a 6bit flash adc,but i have no idea of these above problem,
where can i find document about these question?
help !!!

 

[shiowjyh]

Dear all,

Please note a key item, latch is level sensitive but flip-flop is edge sensitive...

Regards,

what is (are) the difference between latch and flip-flop?

The Flip-Flop is consist of a master latch and a slave latch, the enable pin of these two latch is invert, so the Q of the Flip-Flop is changed when clock rising or falling

 

[Karthikeya]

hi
generally followed method is to use a latch and then a r-s ff in a/d converter. latch is used to sense a small voltage change and produce a large output signal in short time. for high-speed adc's the time from applied input to generate output code is short. if linear circuits like diff amps are used it takes lot of time to reach the desired output value. a latch can amplify(not correct term) the signal in very short time. since it is a level-sensitive and output is desired to stay stable till next clock cycle a ff is used next.

regards

 

[ocarnu]

is it necessary package in order to test the adc chip?
how to chose the means of pacakging?
how to know the size of the capacitance load?
what kind of instrument that i need to test the chip?
i heard that it is hard to test an adc chip
i am designing a 6bit flash adc,but i have no idea of these above problem,
where can i find document about these question?
help !!!

1. No, you can use a probe station if you have one. Anyway you have the pads and probe station needles.
2. High frequency packaging has smaller C/L at pins, smaller footprint, etc. Check the offer (i.e. MOSIS website).
3. For pins is given by package spec, for PCB compute by hand, for logic analyer is in the manual and is written on the fron panel, for the pads, extract, or approximate by hand. Put several pF more, you never know.
4. At least a logic analyzer, some clean DC source, clock gen (or crystal osc) with low jitter, signal gen., a very clean one. For 6b is not a problem though. You can also filter the input signal with a BP filter. If you can lock clock and input signal toghether with different ratios, is very good.
Higher the speed, more difficult is the testing (also expensive).