Why do we need to run typical corner for signoff?

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childs

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Fast corner gives the most pessimistic scenario for hold test; while slow corner gives the most pessimistic scenarioo for setup test.

Why do we need to run typical corner for signoff?
 

hello,
I can't understand well the word 'corner' used here, 'cause English is not my mother tongue. I ever met it before when reading books, and even I can't find a reasonable meaning in dictionary. Would u plz explain it? Thx very much!!

Best Regard,
Wayne Leo
 

Are you asking for STA or simulations?
 

childs said:
Fast corner gives the most pessimistic scenario for hold test; while slow corner gives the most pessimistic scenarioo for setup test.

Why do we need to run typical corner for signoff?
Click to expand...


There are always possiblities of timing violation in typical coner, although wc and bc were passed through timing-simulation.
 
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    ivlsi

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to be more confident on your design!
 

Sometimes, we may have hold time violations in typical corner, even it is ok in fast corner.

By the way, for the corner, it means the RC effection, eg: rcbest, rcworst ...
 

So when both fast & slow corners are clean, can we assume the typical corner shall only have low violations?
 

If MAX and MIN are clean there cannot be any violations at TYP unless your library is broken.
 

randyest said:
If MAX and MIN are clean there cannot be any violations at TYP unless your library is broken.
Click to expand...

@randyest,
Can you explain it little bit more?
 

Delay is monotonic between MIN and MAX (that is, it doesn't go up and down, just up, as process / voltage / temperature changes from MIN to MAX.) So it's mathematically impossible to have a timing violation that occurs only at TYP, assuming synchronous logic. Maybe in asynchronous (unclocked) logic it's possible.
 

hi randyest, because I am using on-chip-variation mode (synopsys), it assume the silicon fabricated is conincidently having very bab timing scenario, which assume:
- for setup test: data path max, clock path min
- for hold test: data path min, clock path max
Does such setting made it possible for some timing in TYP corner being missed out by MAX n MIN corners?

*min = fastest, max = slowest
 

childs said:
Does such setting made it possible for some timing in TYP corner being missed out by MAX n MIN corners?
Click to expand...
I honestly cannot see how or come up with an example of a TYP timing violation that would not also be a violation at MIN or MAX, even when considering OCV or even temperature inversion. Of course I'm basing this on the way my company characterizes cells for our libraries (I work for a large ASIC vendor and have taped out dozens of chips, and I've never checked TYP STA.) But maybe it's possible to have a TYP violation not caught at MIN/MAX at some other vendor who maybe has some different way of making libs? I can't say for sure about every fab/vendor. We do check MIN and MAX and temperature inverted MIN and MAX for sign-off, but never TYP.

I would be very interested to hear an example situation that violates at TYP but not MIN or MAX.
 

I think we do not need run typical corner when MIN/MAX are all pass.
MIN/MAX Signoff and MIN/TYP/MAX Signoff.
 

Just improve confidence. if bc&wc pass, tc should pass too. or library error
 

Thanks for inputs from everyone.

I also heard there is possible some violations might happened during TYP corner even though MIN & MAX both went well. However, it is commonly agreed that such violations (during TYP) are less likely to happen, and even it does, it shall not be huge.
 

still ther will be chacnes to see vioaltion, even min/max are passed.

to be precisily, between min to typ and typ to max, there can be violations, so we are thinking of doing Statistical STA to find out missed violations across the corners
 

 
the std cells in data path and clock paths do NOT scale linearly across different corners, so it's possible you'll see some new violations in typical corner or even in slow corner.
 

Hi,
fast corner gives most optimistic results while slow corner gives most pessimistic results. Timing is closed on typical corner while even considering fast and slow because in practical environment situations it is the typical condition that the IC is in in most cases. Hence many setup/hold violations in fast/slow corners may never appear in real life atall and in many cases are even ignored. Hence if typical corner timing is closed we can assume that the chip will work properly in real world under realistic situations.
 
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