why do we need to give source clock while defining generated clock?

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electronab

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why do we need to give source clock while defining generated clock? Is it just for getting divide_by information or something more. what relationship maintained between the two. For below mentioned two cases -

CASE1 - We do not want to balance master clock and its generated clock.
CASE2 - What if there is another master clock in between master-clock-1 and generated clock (generated from master-clock-1). How would the tool behave?

(I am thinking in terms of physical design tool)
 
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The sta will know the relation between the source clock and the generated ****, and could be considered as synchronous.

---------- Post added at 09:06 ---------- Previous post was at 09:06 ----------

instead two create clocks, that are considered as asynchronous.
 
What if there is another master clock in between master-clock-1 and generated clock
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What do u mean? wanna elaborate?

could be considered as synchronous
Click to expand...
Is it possible to define a latency for the generated clock?
 

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